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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
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Old 1st September 2017, 05:32 PM   #1581
Mike Gergen is offline Mike Gergen  United States
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Are you able to measure the phase noise?
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Old 1st September 2017, 06:44 PM   #1582
1audio is offline 1audio  United States
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
Quote:
Originally Posted by ambrosia168 View Post
5.6448M SC-3, 11 dBm output.
Impressive performance, really at the noise floor of the HP3048 HP 3048A What did you use as a reference oscillator? That system doesn't support cross correlation so the reference oscillator is critical.

That link is a great intro into phase noise measurement. The 3048's core is a box with mixers and a low noise preamp + other stuff to drive a PLL. The system also uses a PC and spectrum analyzers and synthesizers. Lots of stuff.
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Old 2nd September 2017, 05:37 AM   #1583
ambrosia168 is offline ambrosia168  China
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
It's Pierce, not Driscoll. If Driscoll circuit was used, the phase noise could be better. The Q is about 2.3M. Thanks.
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Old 4th November 2017, 10:29 PM   #1584
hollowman is offline hollowman  United States
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Andrea_mori (or anyone who knows):

First, nice work on this project!

Questions:

I'm looking over the PDF plans (found elsewhere in this thread) for the Driscol, Clapp, Pierce oscillators now

I see that the value of capacitors (e.g., C1, C2) vary based on crystal frequency.
Did you compute the suggested values using a formula (equation)? Or did you look them up in a table or spreadsheet?

Thx!
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Old 5th November 2017, 01:07 AM   #1585
andrea_mori is offline andrea_mori  Italy
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The Well Tempered Master Clock - Building a low phase noise/jitter crystal oscillator
Quote:
Originally Posted by hollowman View Post
Andrea_mori (or anyone who knows):

First, nice work on this project!

Questions:

I'm looking over the PDF plans (found elsewhere in this thread) for the Driscol, Clapp, Pierce oscillators now

I see that the value of capacitors (e.g., C1, C2) vary based on crystal frequency.
Did you compute the suggested values using a formula (equation)? Or did you look them up in a table or spreadsheet?

Thx!
For the Clapp oscillator you can use these formulas:
C1 = C2 >= 1000 / f0 in pF for fundamental crystals
C1 = C2 >= 1000 / f3rd or f5th in pF for overtone crystals
L4 = 1 / (6.28 * (>f0)) ^2 * C2 in Henry for 3rd overtone crystals
L4 = 1 / (6.28 * (>f3rd)) ^2 * C2 in Henry for 5th overtone crystals

For the Driscoll oscillator use these formulas:
L4-C1 tuned just above the resonance of the crystal
L2 any value larger 2 to 20 times the reactance than what will resonate with the crystal's C0
R1 has to be choosen as a ratio to R, so as to provide enough gain for the circuit to oscillate. The crystal's ESR increases, the higher the value of R1
A starting point could be ESR * 20 in ohm. High ESR such as 40-50 ohm or more (SC-Cut cystals) needs active device (Q1) with higher hfe
L4 should be selected to have a high shunt impedance with respect to R1, and still resonate at or just below the oscillation frequency. A starting point could be an impedance value around 3 times the resistance of R1: (R1 * 3) / (6.28 * f0) in Henry. Then C1 is selected to resonate just above the resonance of the crystal
C2 should be as large as possible to provide a low impedance load and high Q for the crystal (the lower the impedance, the higher the loaded Q, the lower the phase noise), with R2C2 providing a large phase lag without too much gain loss. A starting point could be the following formula: 1 / f0 in MHz * 500 in pF
R2 is selected in the range 150-600 ohm depending on the ESR of the crystal. The higher the value, the higher the phase lag, the lower the impedance, the higher the loaded Q, but the higher the gain loss. If the gain loss is too high the oscillator does not start.
R3 controls the transistor’s DC current and is selected to get the the transistor’s DC collector voltage at half the power supply

You can simulate the results in LT Spice, usually the simulation is enough realistic.
Obviously, after the simulation each oscillator has to be tested in the real world, that's what I have done to define the values indicated in the tables.

Last edited by andrea_mori; 5th November 2017 at 01:14 AM.
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Old 5th November 2017, 03:02 AM   #1586
hollowman is offline hollowman  United States
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A few more quick questions (I'm too lazy to research this thread or the topic!).

In all the clocks I use (or have built), they output a sine wave. Of course, I am ignorant about clocks other than a superficial know-how.

What are the 'Squarer' options for?

Is there any page/post(s) in this thread with o'scope display images of various TWTMC designs and configs?

Thx!
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Old 5th November 2017, 03:38 AM   #1587
hollowman is offline hollowman  United States
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Was going over some osc. tutorials on YouTube.

The vlogger here recommends a snubber for the Vcc pin for the 74-series logic chip:
YouTube--Clock Sine wave/Square wave oscillator
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