Hello
I am asking for help.
I am about to test this circuit that I found somewhere in the internet.
Help me to understand the output voltage.
If I follow this circuit I will be tying the R and L output and hence a mono signal .
Am I correct in the interpretation and how to get around the problem of mono signal ??
thanks in advance
kp93300
I am asking for help.
I am about to test this circuit that I found somewhere in the internet.
Help me to understand the output voltage.
If I follow this circuit I will be tying the R and L output and hence a mono signal .
Am I correct in the interpretation and how to get around the problem of mono signal ??
thanks in advance
kp93300
Pot 2 does not allow a DC coupled output. You can't set the output to 0V (from 3.2V) when all you have available is 0-5V DC; if you had a negative supply you could do it, but then the DAC chip would not work because a 0V output violates its output spec. See the datasheet.
The fact that a diagram carries a label does not mean that the circuit can achieve it, just that the designer hoped that it would.
The fact that a diagram carries a label does not mean that the circuit can achieve it, just that the designer hoped that it would.
I did not use the TDA1543 internal variable bias current sources because this results in increased noise and increased (DC) mismatch between L and R channels. The bias circuit consists of a diode string that develops a certain voltage drop and two variable Op-amp based bias sources. Slight voltage change on the diode string changes the bias current (relatively high sensitivity). So when noise is injected into this steering input it basically gets amplified. Pin 7 is used for both, external reference voltage for an OP-amp I/V for example (datasheet) or for varying the bias current between -0.6mA and +5mA.
The posted schematic shows the basic concept that functions. But the pots can be replaced by accurate, adjustable voltage regulators in order to improve performance.
The idea is to connect both I/V resistors to a bias voltage instead of increasing the TDA1543 bias current. This will result in lower noise and better matching between L and R channel bias current. This trick also works with the TDA1541A in order to null the output voltage, one can either use a +2mA CCS or connect the passive I/V resistor to a bias voltage instead of GND.
DC output compliance (with 5V supply) lies between 1V8 and 3V8 (check datasheet). This allows for max. 2Vpp signal swing and the center voltage would be 3V8 - 1V = 2V8. The bias voltage (pot 1) would then have to be 2V8 + 1V = 3V8. The value of 3V2 in the schematic introduces a marginal increase in even order harmonics that result in a more natural sound with zero order hold output signals, but this is a matter of taste of course. The technically correct voltage equals 3V8.
Anyway, the signal on the TDA1543 output will now swing between 1V8 and 3V8 and the DC level would be 2V8. Without further action a coupling cap would be needed when GND is used as signal reference.
But it is also possible to use a non-zero signal reference, like 2V8 for example since circuit GND does not need to be connected to external circuits.
With the RCA “GND” connection tied to 2V8 instead of 0V GND there will be zero volts DC between this voltage (set by P2 in the schematic) and the 2V8 on the TDA1543 output. We now achieved a DC-coupled output as long as we do NOT connect GND to external circuits and use 2V8 reference voltage instead!
This concept works excellent in practice, I designed and built many different DACs and SD-players that are based on this non-zero "GND" reference voltage in order to obtain DC-coupled output. The SD2-player and UD2 USB DAC (both based on the TDA1541A) use -5V as "GND" reference and a DC servo on each I/V resistor ensures there is no DC offset between -5V and the outputs regardless of chip tolerances. The UD1 (TDA1543 based USB DAC) uses a similar concept as with the circuit diagram I posted, but it also has a DC servo on each output.
These devices drive both transistor and tube power amplifiers without any problems.
(coupling) capacitors have parasitic inductance, capacitance and parasitic resistance. So basically every capacitor is a series resonance circuit where the quality factor is set by the parasitic resistance. These are non-linear devices that will shape a passing frequency spectrum by selective attenuation / amplification. The modified frequency spectrum translates to a changed perceived sound. Since every capacitor has unique properties that can be measured with LCR meters, each capacitor will introduce unique spectrum shaping and a related unique sound.
The published circuit also contains electrolytic capacitors (non-linear) but non-linearity of these components is compensated by paralleling a linear shunt impedance in the form of a potentiometer.
OK, now I understand. The apparent extra resistors are actually the input impedance of whatever follows, although the circuit does not show this.
0V is not ground, even though the circuit shows the ground symbol connected to 0V. The supply (and the digital source, if using SPDIF) must be floating, although the circuit does not show this.
The circuit does not omit the output capacitors; instead it puts a common 470uF electrolytic output capacitor in the ground connection. The circuit is only DC-connected for DC; for AC it uses a cap. The relatively high value of the parallel resistance means that any electrolytic cap problems will be present, including a little LF interchannel crosstalk. Separate electrolytic output caps in the signal lines would be preferable.
It is interesting how people can be fooled. People who would not be seen dead with an electrolytic in their 'signal path' may happily use this circuit, not realising that it breaks all their rules.
0V is not ground, even though the circuit shows the ground symbol connected to 0V. The supply (and the digital source, if using SPDIF) must be floating, although the circuit does not show this.
The circuit does not omit the output capacitors; instead it puts a common 470uF electrolytic output capacitor in the ground connection. The circuit is only DC-connected for DC; for AC it uses a cap. The relatively high value of the parallel resistance means that any electrolytic cap problems will be present, including a little LF interchannel crosstalk. Separate electrolytic output caps in the signal lines would be preferable.
It is interesting how people can be fooled. People who would not be seen dead with an electrolytic in their 'signal path' may happily use this circuit, not realising that it breaks all their rules.
HI Ecdesigns
Thanks for providing more info.
tested this morning.
I can set P1 to get 3.2 V but with P2, i can trim the output to 0.04V maximum .
I have not hooked up the speakers yet.
Is this value of dc at the output acceptable?
HI DF,
This circuit is simple, i build it to hear for myself and make a conclusion after listening .
thanks to all
kp93300
Thanks for providing more info.
tested this morning.
I can set P1 to get 3.2 V but with P2, i can trim the output to 0.04V maximum .
I have not hooked up the speakers yet.
Is this value of dc at the output acceptable?
HI DF,
This circuit is simple, i build it to hear for myself and make a conclusion after listening .
thanks to all
kp93300
It may sound fine, but it isn't really DC-coupled and it doesn't remove caps from the signal path - instead it inserts them in an unhelpful way. Don't believe everything you see on the internet!
The only potentially useful thing it does is avoid using the internal current source (by leaving the REF pin open circuit). However, setting this to zero may or may not actually be better than setting it to some non-zero current, as the internal circuit is still there and (presumably) still doing something.
The only potentially useful thing it does is avoid using the internal current source (by leaving the REF pin open circuit). However, setting this to zero may or may not actually be better than setting it to some non-zero current, as the internal circuit is still there and (presumably) still doing something.
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