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Old 20th March 2014, 10:55 PM   #21
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Ok. How do I slave the source to the DAC?
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Old 20th March 2014, 11:04 PM   #22
Eldam is offline Eldam  France
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Need an output buffer then an input buffer for the clock line or does it need jus a maximum inchees/cm line between the master clock and the slaved device ? speed clock need to be adapted for the slave ?
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Old 21st March 2014, 07:22 AM   #23
Julf is offline Julf  Europe
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Originally Posted by mBox View Post
Ok. How do I slave the source to the DAC?
To start with you need a source that can be synchronized to an external clock (this is normal on pro gear). What is your source?
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Old 21st March 2014, 08:14 AM   #24
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Thanks. I'm using RPi as source - sending the signal to my DAC

SOURCE (RPi) -------USB------> DAC
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Old 21st March 2014, 08:42 AM   #25
Julf is offline Julf  Europe
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Thanks. I'm using RPi as source - sending the signal to my DAC

SOURCE (RPi) -------USB------> DAC
OK, but that is asynchronous USB, so there is no need to synchronize the clocks. The clock synchronisation is an issue only for connection methods (such as S/PDIF) that don't have a flow control mechanism.
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Old 21st March 2014, 02:37 PM   #26
Eldam is offline Eldam  France
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Julf,

If the master clock is the one of the main DAC : do we need to adapt the frequency clock with dividers to feed the emmiter spidf chip in the source side ? Let say with a RPI as well (it's just to understand, have 2 SB Duet, but don't want to break those device with my bad skill).

I have maybe please a more general question about the clock wires: which is the "worse" solution at same length of cables if we can put the two devices close enough together):

1- spidf feeding with buffers (and/or multiple serie chips or passive components in serie)
2- High jack the I2S from the source if possible ? Of course with a flat SgSgSgSG wire : S(ignal)/g(round) ?

My actual understanding is 1) is a good enough solution but 2) a better one as the clock has its own non shared line (but doesn't work if length is > at something like 5 cm) ?
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Old 21st March 2014, 02:46 PM   #27
Julf is offline Julf  Europe
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If the master clock is the one of the main DAC : do we need to adapt the frequency clock with dividers to feed the emmiter spidf chip in the source side?
I would definitely not start to fiddle with the spdif clock unless it was clearly shown that there is an issue with excessive jitter.
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Old 21st March 2014, 02:56 PM   #28
Eldam is offline Eldam  France
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thank you,

Ok, my understanding with your answer is a spidf receiver can work with a large bench of frequencies.

It was as just more a theoric question as I'm planning to play with old miltibit dac chips. But have two SPIDF Sure electronics spidf W8804 receiver. Those devices are nice for fools like me : very versatil : you can switch off the hardware mode... But was very addict to the Ecdesign thread one year ago; the parts with the masterclock and buffers was a little hard to understand and I gave up...
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Old 21st March 2014, 03:02 PM   #29
Julf is offline Julf  Europe
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Ok, my understanding with your answer is a spidf receiver can work with a large bench of frequencies.
Definitely!
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Old 31st March 2014, 09:23 AM   #30
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Does anyone know a good (cheap) USB to S/PDIF converter?
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