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Old 31st January 2014, 09:28 PM   #1
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Join Date: Mar 2012
Default jitter possible problem?

Hi guys.
I need your advice. Iam working on one project where i will have lot of adc's and dac's routed cross cpld. Each converter will be on separated card and all card's will be clocked via word clock which will be distributed by back plan. On each card will be pll and multiplicator and divider. So each card will have synced lrclk, bclk and mclk.

And my auestion is: do you think it is a good idea to sinc cards with word clock (96kHz) and send i2s data separately? Maximal length of bus about 50cm and bus is surrounded ground planes.
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Old 1st February 2014, 04:10 PM   #2
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Join Date: Jun 2009
You're asking if there'll be meaningfully lower jitter from routing sclk, lrclk, sdan, wclk between cards as opposed to just sclk, lrclk, sdan with wclk extracted from lrclk? Depends on the clock distribution graph, I2S routing, PLL bandwidths, performance requirements, and why additional clock multiply and divides are occurring outside the PLLs. As posed the question seems too loosely defined to be usefully answerable. So you'll probably get better responses if you're more specific.
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