CS8412 to EIAJ or I2S - diyAudio
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Old 17th December 2013, 06:59 AM   #1
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Default CS8412 to EIAJ or I2S

It's been ages since I used a CS8412, but I've forgotten my basic DIYs and am lazy anyway ... it's easier to pose a dumb query here as I'm sure the answer is easy for many of you...

I've got two DAC types:

Philips TDA1545A (accepts only EIAJ data)
Philips TDA1543, TDA1541A (accept only I2S data).

EIAJ and I2S are, of course, incompatible signal formats. So for a Philips CDP I have that came with stock TDA1543, I had to create a special I2S-to-EIAJ converter (using a bunch of 74HCs, etc) to get the CDP's decoder to "talk" to the EIAJ-based TDA1545 DAC.

However (and TTBOMK), all schematics that I've seen using CS8412 + TDA1545 or CS8412 + TDA1541/TDA1543 have direct connections for the WS (FSYNC), CLK, DATA lines.

How does one config. the CS8412 to spit out I2S or EIAJ signals ... or am I missing something obvious?

Thx!!
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Old 17th December 2013, 08:22 AM   #2
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Use TDA1387T (SOT96-1) which is a smd variant of TDA1545A that can accept I2S signal directly...no glue logic needed.
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Old 17th December 2013, 08:30 AM   #3
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The CS8412 has various output modes and yes it can be configured to drive both EIAJ and I2S without needing any glue logic. Table 3, page 24 is the relevant one. You'll note that mode 2 is I2S compatible and I seem to recall mode 5 works with TDA1545A.
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Old 17th December 2013, 08:40 AM   #4
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Default Stay ON-TOPIC, please!

Quote:
Originally Posted by aparatusonitus View Post
Use TDA1387T (SOT96-1) which is a smd variant of TDA1545A that can accept I2S signal directly...no glue logic needed.
Right ... but that's not what I asked...

Rather ...
If I want to use a EIAJ DAC (TDA1545A), why, do I have to to CONVERT to EIAJ in a CD player that orig. has an I2S-based DAC (TDA1543, TDA1541, etc.)? I.e., the CD player's decoder only spits out I2S.

But ... (and by all means correct me if I'm wrong)...
Why don't I have to convert to EIAJ (or I2S) for any-format DAC (TDA1454, TDA1543/41) if I am using a Digital Audio Interface Receiver IC, like CS8412, that also spits out the same three-signal lines (WS, CLK, DATA).
Or is there some set pin or other simple config. on the Receiver chip that allows one to select its output format .... or do Receivers like CS8412 spit out some kind of "universal" one-size-fits-all datastream that makes my query moot?
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Old 17th December 2013, 08:46 AM   #5
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Quote:
Originally Posted by abraxalito View Post
The CS8412 has various output modes and yes it can be configured to drive both EIAJ and I2S without needing any glue logic. Table 3, page 24 is the relevant one. You'll note that mode 2 is I2S compatible and I seem to recall mode 5 works with TDA1545A.
Thx ... I'll ck that out ...

One more somewhat-related query:
Do any of these Receiver ICs, like CD841x, also have WS/CLK/DATA as inputs (i.e., in addition to the usual SPDIF-data input)? ... this would allow them to be used as a one-chip I2S <--> EIAJ converter.
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Old 17th December 2013, 08:50 AM   #6
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None that I'm aware of. I have a schematic on my blog which with the addition of a single flip-flop can be used to do I2S-EIAJ conversion. Its a handful of cheap logic though, not a single chip.
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Old 17th December 2013, 11:51 AM   #7
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The almost-"single"-chip design proposed on this forum some time ago does not work, as I noted in that same thread.

I was able to get the following to work:
Click the image to open in full size.
...but it's hardly compact or elegant, on my Veroboard version:
Click the image to open in full size.

There is a marketed version that came out not too long ago from diyparadise ...it may use fewer ICs (can't see other side of PCB, so not sure about components used)...
Click the image to open in full size.
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Old 17th December 2013, 01:21 PM   #8
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If minimum chip count is your aim then Tam Lin's schematic (left in the comments on my blog) is easily the winner - it would probably need just one extra half-chip to delay WS by a single clock cycle. It is however considerably more expensive and power hungry than my own solution.
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Old 17th December 2013, 03:12 PM   #9
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Quote:
Originally Posted by abraxalito View Post
If minimum chip count is your aim then Tam Lin's schematic (left in the comments on my blog) is easily the winner - it would probably need just one extra half-chip to delay WS by a single clock cycle. It is however considerably more expensive and power hungry than my own solution.
I don't know enough about the Lin design to tell if it'll work. My prev. experimentation with a several diff. designs utilizing fewer logic ICs did not work.

BTW ... from that same blog page, looks like you took a crack at this issue yourself (??) here ...
Click the image to open in full size.
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Old 17th December 2013, 03:16 PM   #10
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Yes, that was my second build of the device whose schematic is shown (albeit with one correction). Still working fine.
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