What is the difference ? Pours copper ground is the action, ground plane is the layout of difference GROUNDs. Is it correct ?
50MHz is not high speed, 1GHz above is considered as high speed.
Extract from the above PDF
Some PCB Designers do this as a matter of habit stating that they have always done this for various reasons. Also, many reference designs supplied by chip manufacturers use this ground pour technique so you may need to follow their recommendations if you want the design to work
especially at high speeds – WRONG!
In conclusion, ground pours may be effective on high impedance, analogue two layer boards but do not significantly reduce crosstalk on high speed, low impedance digital multilayer boards. Also, ground pours have the disadvantage of altering the impedance of traces that run adjacent to a ground pour area causing reflections and are therefore not recommended for use in the digital domain.
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Besides impedance, how about capacitance ?
ESS' official layout notes (Maximizing DAC Performance for Every Budget) page 5:
http://www.esstech.com/PDF/Application_Note_Component_Selection_and_PCB_Layout.pdf
http://www.esstech.com/PDF/Application_Note_Component_Selection_and_PCB_Layout.pdf
Thank you for interesting in my pcb
sorry for the late reply, I just found this message.The schematic is following the official datasheet, it can be download from the website directly. The improvement is limitless for diyer. asynchronous MCLK, battery power, film capacitor and many more we have never think of. Welcome to share your modification to all of us
Hi DIYINHK - I also have this board. I see you have now stocked some NDK ultra low phase noise oscillators - at 49.152MHz and 45.1584MHz. I have one question really - can one of these be used on the ES9023 board for async MCLK operation - will they be fine running at 3.6v and which one would you use?
How will this affect the DAC if I'm using the XMOS 384kHz USB/I2S converter, will it affect this at all (I wanted the async to have the option to connect directly to Raspberry Pi I2S GPIO pins)
How will this affect the DAC if I'm using the XMOS 384kHz USB/I2S converter, will it affect this at all (I wanted the async to have the option to connect directly to Raspberry Pi I2S GPIO pins)
High speed is defined by the rise time of the digital wave. %)MHz you had better lay out properly or you are going to have trouble.
Copper pours are not ground plane, a ground plane is a full contiguous layer of copper adjacent to the signal layer, usually for best results you are best having an unbroken ground plane next to every signal layer, if this is not possible run your critical signals on the layer next to the ground plane.
Rubbish, high speed digital (above 1MHz) is better with a contiguous path underneath for return currents.
If you have a contiguous power plane, this can also be used for the return path for signals.
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Are you kidding ?
In 1974, the clock speed of Intel 8080 is 2MHz. If you thing high speed digital (above 1MHz), you seem living in dinosaur age.
No and I do high speed digital layout everyday. Do you know what actually makes a design high speed, no I didn't think so, but it is not the clock frequency that a device is running at.
As I said any digital above 1mHz benefits from a full contiguous ground plane.
Now the chances are I do know an awful lot more about laying out digital circuits than you do, and no I am not living in the dinosaur age, so unless you know what you are talking about don't patronise me.
As I said any digital above 1mHz benefits from a full contiguous ground plane.
Now the chances are I do know an awful lot more about laying out digital circuits than you do, and no I am not living in the dinosaur age, so unless you know what you are talking about don't patronise me.
Really,
Can you find any contiguous power plane in a Apple II 1MHz HIGH SPEED COMPUTER ?
What kind of EDA software are you capable of ?
Today, it seems that people like you only capable to desgin multi-layer PCB with power plane and ground plane and don't know how to desgin a single layer PCB.
Can you find any contiguous power plane in a Apple II 1MHz HIGH SPEED COMPUTER ?
What kind of EDA software are you capable of ?
Today, it seems that people like you only capable to desgin multi-layer PCB with power plane and ground plane and don't know how to desgin a single layer PCB.
You are talking utter bull mate.
I can design any sort of PCB and do. What has a single layer PCB got to do with digital, you need at least 2 and preferably more. Todays EMC requirements, as well as signal integrity requires a ground plane for return currents for digital.
Apple II has no relevance today, why mention it.
How do you define high speed, you have not answered...
As to EDA tools, Cadstar mainly and Allegro very occasionally.
I can design any sort of PCB and do. What has a single layer PCB got to do with digital, you need at least 2 and preferably more. Todays EMC requirements, as well as signal integrity requires a ground plane for return currents for digital.
Apple II has no relevance today, why mention it.
How do you define high speed, you have not answered...
This shows you do not know what you are talking about. What do you mean people like me, I am a professional PCB designer who works on a lot of high end designs and have done over many years, boards I did in the late 80's were used to control the magnetics on the Daresbury accelerator when they were upgraded in 1990ish, so I have been working at the sharp end of PCB layout for many years now and still am, as well as advising companies on such subjects as design for signal integrity/EMC and specialising in SMPS layout for really critical designs.
As to EDA tools, Cadstar mainly and Allegro very occasionally.
I asked you a question regarding what is high speed digitals definition. Now you come back with this inane question, after referring to an Apple motherboard that has NO relevance today.
The rise time of any signal is determined by the logic being used to generate the signal, if you look you can find a graph of logic familys and increasing rise times over the years, this will give you some hints as to why most digital layout these days is best considered high speed. When you get on to interfaces that are not only high speed due to the rise time but have very fast clocks then layout becomes even more arduous, an example of this are the various DDR memory interface. Even the lowly USB has to be routed as differential pairs with a max 1mm skew.
The ever decreasing silicon size, the ever decreasing working voltages, less than 1V for some logic all makes for faster logic but has effects on both layout and the increasing high frequency spectral content of 'square' waves.
So you question is akin to 'how long is a piece of string' as fast or as slow (within reason) as you want.
The rise time of any signal is determined by the logic being used to generate the signal, if you look you can find a graph of logic familys and increasing rise times over the years, this will give you some hints as to why most digital layout these days is best considered high speed. When you get on to interfaces that are not only high speed due to the rise time but have very fast clocks then layout becomes even more arduous, an example of this are the various DDR memory interface. Even the lowly USB has to be routed as differential pairs with a max 1mm skew.
The ever decreasing silicon size, the ever decreasing working voltages, less than 1V for some logic all makes for faster logic but has effects on both layout and the increasing high frequency spectral content of 'square' waves.
So you question is akin to 'how long is a piece of string' as fast or as slow (within reason) as you want.
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