Low jitter I2S buffer?

SunShade · 1st April 2013, 04:03 PM

What is the best way to buffer I2S signals (clock, data) without adding jitter ?
Is it better to use a line driver or a Smitt trigger or maybe something else?

oshifis · 2nd April 2013, 01:53 PM

To what distance do you want to carry the I2S signals? I read somewhere in this forum that a small (100 ohms?) resistor in series at the source will prevent reflection. Reclocking at the receiving end would also be an option.

twest820 · 2nd April 2013, 05:12 PM

If you want low additive jitter look at clock distribution buffers. If you're recovering MCLK from I2S output quality is likely dominated by the recovery PLL's jitter, so this may not be the most useful optimization. If the clock transition's handled with an ASRC time domain ringing from brickwall antialiasing is likely the dominant source of subjective degradation.

oshifis is referring to source termination on a relatively stiff transmission line, which is a common mechanism for mitigating ISI in two layer audio PCBs. There's plenty of existing material available from searching on termination schemes, characteristic impedances, and reflections if one wants more context on that.

1st April 2013, 04:03 PM	#1
SunShade diyAudio Member Join Date: Nov 2004 Location: Italy	Low jitter I2S buffer? What is the best way to buffer I2S signals (clock, data) without adding jitter ? Is it better to use a line driver or a Smitt trigger or maybe something else?

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2nd April 2013, 01:53 PM	#2
oshifis diyAudio Member Join Date: Mar 2004 Location: Budapest, Hungary	To what distance do you want to carry the I2S signals? I read somewhere in this forum that a small (100 ohms?) resistor in series at the source will prevent reflection. Reclocking at the receiving end would also be an option.

2nd April 2013, 05:12 PM	#3
twest820 diyAudio Member Join Date: Jun 2009 Location: Orygun	If you want low additive jitter look at clock distribution buffers. If you're recovering MCLK from I2S output quality is likely dominated by the recovery PLL's jitter, so this may not be the most useful optimization. If the clock transition's handled with an ASRC time domain ringing from brickwall antialiasing is likely the dominant source of subjective degradation. oshifis is referring to source termination on a relatively stiff transmission line, which is a common mechanism for mitigating ISI in two layer audio PCBs. There's plenty of existing material available from searching on termination schemes, characteristic impedances, and reflections if one wants more context on that.