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Old 20th March 2013, 10:07 AM   #1
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Default XO clock "load"

For experimental clocks or XOs, I want to put a "load" in front of it (w/o using intended ICs such as DACs or decoders). In other words, I want the clock to behave as it were in situ of its normal topology.
How does one effectively/cleanly load the clock using simple/passive components? E.g, via resistor, cap, etc. on the clock output.
The result of such an experimental setup should be some sort of breadboardable ckt that can be easily part-swapped (tweaked) whilst on the oscilloscope.

Thx!
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Old 20th March 2013, 02:33 PM   #2
marce is offline marce  United Kingdom
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For both you have to take into account the PCB parasitics especially, or if using cable the cable impedance mismatches etc. The best way of doing this is using high speed simulation software, then the clock and any terminating resistors can be modeled to match the real life conditions, otherwise any results are pretty meaningless.
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Old 20th March 2013, 02:50 PM   #3
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Quote:
Originally Posted by marce View Post
For both you have to take into account the PCB parasitics especially, or if using cable the cable impedance mismatches etc. The best way of doing this is using high speed simulation software, then the clock and any terminating resistors can be modeled to match the real life conditions, otherwise any results are pretty meaningless.
This may be overcomplicating things ... at least for the time and effort I want to put into a project
Another way to "model" this is to know what the "nominal" input impedance of the X_in (clock input pin) may be. Anyone want to take a shot?
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Old 20th March 2013, 02:53 PM   #4
qusp is offline qusp  Australia
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I suspect it will be different for each different DAC chip topology and model
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Old 20th March 2013, 03:09 PM   #5
DF96 is offline DF96  England
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The DAC datasheet may tell you about the chip. The PCB track may dominate this, though.

Loading the oscillator is clearly a much simpler problem than designing the oscillator, so I wonder what sort of experiments you are planning.
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Old 20th March 2013, 03:43 PM   #6
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Default Using a simple clock

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Loading the oscillator is clearly a much simpler problem than designing the oscillator, so I wonder what sort of experiments you are planning.
Nothing fancy. I've got to keep the design simple and as compact as possible as it will occupy some tight real-estate. Namely, for use w/ PC sound cards (see Xonar ST thread elsewhere). I have 12v avail from Molex. I was thinking something like this...
Click the image to open in full size.
One can't easily tweak/prototype in and around PC cards so that's why I need an on-the-bench/breadboard solution.
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Old 20th March 2013, 04:21 PM   #7
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Nothing fancy.
Unfortunately I doubt that anything less than fancy will suffice.

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The result of such an experimental setup should be some sort of breadboardable ckt that can be easily part-swapped (tweaked) whilst on the oscilloscope.
I fear that anything 'breadboarded' is likely to suffer from problems due to strays and other inconsistencies which will make any results meaningless in terms of true high performance.

If I were embarking on such an investigation I would anticipate needing well designed PCBs and highly repeatable conditions to evaluate component changes. I would expect to iterate the PCB more than once and see differences due to those changes alone.

A test setup capable of revealing meaningful differences in jitter at the levels which are the current SOTA will not be cheap, it is beyond the capabilities of the average 'scope. You need a lot of resolution, storage, and a software suite purposed to the task. You might alternatively test in situ but that would require a dedicated audio test set, such as the Audio Precision, and completely respinning the target board to accommodate the changes.
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Old 20th March 2013, 04:38 PM   #8
marce is offline marce  United Kingdom
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Having routed many many clocks, the only guaranteed way is simulation, you can then match any termination required to the actual PCB and hence get the best integrity of the clock signal, that is if you want ultimate fidelity of the clock signal, and when distributing a clock it becomes a necessity. A lot of the ad-hoc modifications I see on here to clocks will cause more problems than they solve.
The basic rules for clocks (any) are short traces, as short as humanly possible, isolation from noise, and avoid any cables or traces that create an integer divideable fraction of the wavelength (again the wavelength is determined by the layout and the dailectrics used, whether the route is microstrip or stripline etc etc), 1/10 1/20 1/4 1/2 avoied like the plauge.
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Old 20th March 2013, 04:56 PM   #9
DF96 is offline DF96  England
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For audio purposes about the only thing that matters is jitter, but that is hard to measure and depends far more on oscillator design and crystal quality than external loading. If you are worried about loading then you can always add a buffer.

I still don't know what you intend to do. I suspect you don't know either.
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Old 20th March 2013, 05:32 PM   #10
marce is offline marce  United Kingdom
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Again this can be affected by the layout. Buffers can be even more of a nightmare, the drive current can be quite hard causing ringing and other problems and often require more careful matching than an unbuffered clock.
But most of this is moot unless you are going for the ultimate in clock signal fidelity as equipement usually works, and as we often dont have the tools to measure it can imagine these beautiful clock signals traveling down a few inch of wire and improving everything...
Excuse my cynicism.
Oh if you want to find out the loading (real) a device presents you are probably better of getting hold of the IBIS data for a device.
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