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Old 20th March 2013, 06:31 PM   #11
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Default Vanguard tcxo oscillator in PC

Thx for your inputs .... stuff to think about.
As far as the experiment ... i.e, what do I REALLY want to do?
Simply: Deliver clean power to a Vanguard tcxo oscillator.
Something a bit better than this:
Click the image to open in full size.
Remember this is for a PC. And pulling that audio card out to tweak -- never mind trying to stick a probe on it in situ -- is not ... uh ... convenient
I'm not looking for SOTA clock performance. I'll even be willing to not 'scope the output of the XO if my scope is not up to the task. Rather, I could take scope measurements as far as the PSU/reg output -- tweaking that part of the ckt as much as possible. The XO I have is 0.1ppm Vanguard TCXO, which others have favorably commented on. The simple Tent ckt from #6 (above) is also okay for me -- I've used it before.
Still, for tweaking purposes, methinks the XO should feed something on its OUT pin. How about something as simple as ,say, a 10pf poly cap + resistor ... to ground?
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Last edited by hollowman; 20th March 2013 at 06:39 PM.
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Old 21st March 2013, 07:14 AM   #12
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Default Short traces vs. speed of "light"

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Originally Posted by marce View Post
The basic rules for clocks (any) are short traces, as short as humanly possible, ....
Is this because the of shorter travel time (even at or near c) is important given the scale of clock pulses ... and/or ...because the addit. trace/wire/etc. picks up noise?
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Old 21st March 2013, 12:28 PM   #13
marce is offline marce  United Kingdom
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Both, for a fun view of the problemm from the other side of the coin have a look at this:
The 10 Best Ways to Maximize Emission from Your Product
Basicly the clock is the most important signal, all other timing events are controlled by this signal, the longer the trace, as you have said the more likely it is to pick up noise, pollute other signals, have impedance mismatches, ISI (inter symbol interference), the loop area is bigger etc etc.
if you are routing clocks on a PCB thenthe spacing round a clock should be 3S min, where S is the normal track to track spacing, this allows you to run a guard track round the clock signal.
The following link shows a good example of impedance mismatch on your clock signal, and some other graphical examples of what happens to the poor clock signal when badly treated:
http://www.digikey.co.uk/Web%20Expor...f?redirected=1
The above photograph is a good example of how not to do it, while the clock connection might be short we have an ariel fastened to the VCC pin, and by the looks of it no local decoupling.
Remember the clock is queen, the king being 0Vs (GND return)
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Old 21st March 2013, 12:33 PM   #14
marce is offline marce  United Kingdom
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The Velocity factor of any signal is found by Vf=1/Sqare Root of Er. (approx 4.2 for FR4, outer layer traces the signal propogates faster than inner layer traces, a factor to remember when doing length matching).
Trace length should only be increased when required such as DDR interfaces where it has to be in relation to the longest data and address lines, for standard clocks always minimise the distance. More boards fail EMC due to clock routing and length than almost any other cause, this noise will also effect the signals on the actual PCB its self. EMC and signal integrity are two sides of the same coin.
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Old 21st March 2013, 03:26 PM   #15
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I think the tight real-estate in PC cases and the SC naturally force one to use short paths. The OUT pin of this osc. is essentially at the decoder pin:
Click the image to open in full size.

BTW: Found what I may have been querying about (it was on the eBay sale page for the Vanguard osc!):
Click the image to open in full size.
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Old 23rd March 2013, 02:35 AM   #16
Eldam is offline Eldam  France
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Hi,

Have you please a link for the simulation software you talk about ?

Can this scheme upon (page 1) from Tentslab website may be use with two outputs (Masterclock) ?
Do we have to use a buffer if one of the load is not near the XO (few inches to the source : streamer or cd player) ? (one output buffer near the XO and one input bufer near the load?)...after reading your two interesting links, it seems to be impossible to reclock better a ready made device without a lot of ressources (pcb design, measurement) !

Last edited by Eldam; 23rd March 2013 at 02:49 AM.
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Old 23rd March 2013, 03:44 AM   #17
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Default External clocking and reclocking

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Originally Posted by Eldam View Post
Can this scheme upon (page 1) from Tentslab website may be use with two outputs (Masterclock) ?
Do we have to use a buffer if one of the load is not near the XO (few inches to the source : streamer or cd player) ? (one output buffer near the XO and one input bufer near the load?)...after reading your two interesting links, it seems to be impossible to reclock better a ready made device without a lot of ressources (pcb design, measurement) !
Search for 'XO clock' within diyaudio.com and you'll come up with several hits. I've made something similar to Tent's XO-DAC clock here ...
Click the image to open in full size.
...with a re-clocker (buffer) ckt, and it did improve SQ despite the added complexity (= greater trace mileage, etc.). I view a dedicated (outboard) clock/re-clocker as necessary evil: perhaps, two steps bwd and three fwd.
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Old 23rd March 2013, 10:27 AM   #18
marce is offline marce  United Kingdom
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The one I use:
CADSTAR Signal Integrity Verify
another
Signal Integrity Analysis, Design & Simulation Tools | HyperLynx® - Mentor Graphics
Cadences offering:
Cadence Allegro PCB SI
and just for fun:
AC/DC Module | Simulation Software
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Old 24th March 2013, 01:14 AM   #19
Eldam is offline Eldam  France
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I already search... but i'm just in the beginning in the puzzle, twest820 give me usefull answers too.

thanks guys
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Old 28th March 2013, 05:23 AM   #20
sidiy is offline sidiy  Canada
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Hello hollowman,
A couple of people here &elsewhere have posted on several occasions a caveat concerning these tall-ish looking TCXOs (marketed by some chinese sellers as "low jitter" - they're quite the opposite). Inside you will find 2 pcbs: one containing a pullable VCXO at 19.2MHz or 19.8MHz most likely with a TC compensating network on the control pin; the other having a PLL multiplier circuit like the one linked in this post

...You have already two reasons why it can't be low-jitter. Luckily some professionally made measurements of these contraptions can still be found somewhere on the forum where you're no longer a member.

Best luck with your project.



Quote:
Originally Posted by hollowman View Post
I think the tight real-estate in PC cases and the SC naturally force one to use short paths. The OUT pin of this osc. is essentially at the decoder pin:
Click the image to open in full size.

BTW: Found what I may have been querying about (it was on the eBay sale page for the Vanguard osc!):
Click the image to open in full size.
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