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-   -   Stopped Clock Operation (AN-207) (http://www.diyaudio.com/forums/digital-line-level/228527-stopped-clock-operation-207-a.html)

LuisMCP 24th January 2013 05:55 AM

Stopped Clock Operation (AN-207)
 
5 Attachment(s)
Circuit1 can be seen on Analog Devices Application Note AN-207. It is named “Stopped Clock Operation” and it was developed for AD1856 DAC.

I2S signal (CLK, WCLK, DATA) is changed to two signals (CLK1, LE, DATA) and (CLK2, LE, DATA) for feeding DACs for channels L and R.

I saw this circuit which was a good candidate for a Non-Oversampling PCM1704 setup, with a simplified and elegant glue logic.

Circuit2 was the actual circuit that I made to apply the Stopped Clock Operation. In my first tests, this not works at all, and I don’t know was the matter.

One difference between AD1856 and PCM1704 seems timing table, but I’m not sure.

Any suggestions are welcome.

Tam Lin 24th January 2013 03:39 PM

The AN circuit outputs left-justified data. The PCM1704 expects right-justified data. Unless the I2S input has 24-bit sub-frames the circuit will not work. Even then, the PCM1704 is fussy about stopped-clock operation. RTFDS

josiphal 24th January 2013 07:33 PM

PCM* dacs are not working with stopped clock. I2S signal for PCM* (or any other non I2S) dac can be aligned using 74HC164 for data line adjustment.

Tam Lin 24th January 2013 09:29 PM

The PCM1704 certainly does work with stopped clock protocol. It's just fussy about the timing when the clock restarts. RTFDS
Quote:

PCM1704 datasheet
“Stopped Clock” Operation:
The PCM1704 is normally operated with a continuous BCLK input. If BCLK is stopped between input data words, the last 24 bits shifted in are not actually transferred from the serial register to the parallel DAC register until WCLK goes LOW. WCLK must remain LOW until after the first BCLK cycle of the next data word to insure proper DAC operation. The specified setup and hold times for DATA and WCLK must be observed.
The trouble with using the '164 to align the data is it doesn't preserve the phase relationship between BCLK and DATA.

josiphal 25th January 2013 12:13 PM

A universal shifting circuit for interfacing decoder X with converter Y.
DAC with two PCM1704

LuisMCP 14th February 2013 05:39 AM

Thanks Folks!
You are right, I have implemented the Universal Shift Register and it works fine !

Only remains a serious problem with hum. Huge hum. It seems that Sen I/V converter is the source of hum. Hum is there also when DAC is off. If I unplug the power cord, then the hum is gone out and back when plug AC cord.

It seems that floating PSU of Sen I/V is a great candidate for hum source.


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