Hello,
I posted this in a DAC product based thread but thought I'd open it up to a broader audience.
What is the effect of having multiple DAC clocks in a DSP based active speaker set-up?
I am contemplating using a mini DSP to feed 3 x DAC PCB's.
Will freewheeling clock sources cause effective phase shift across the DAC outputs?
I posted this in a DAC product based thread but thought I'd open it up to a broader audience.
What is the effect of having multiple DAC clocks in a DSP based active speaker set-up?
I am contemplating using a mini DSP to feed 3 x DAC PCB's.
Will freewheeling clock sources cause effective phase shift across the DAC outputs?
If the DACs' MCLKs aren't locked to the I2S SCK the result's typically undefined. The exceptions are the clock domain translation provided by the ASRC in ESS parts or DACs with integrated PLLs. (It's also possible the sample and hold block in the AD1955 may offer similar flexibility with somewhat lower accuracy but the datasheet rather implies otherwise. Some Cirrus parts do support arbitrary phase between MCLK and SCK but those do still require the usual integer MCLK to SCK ratio.)
Generally the best I'd expect would be silence with noise being more likely.
Generally the best I'd expect would be silence with noise being more likely.
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I cant for my life understand why a number of DACs, in a multichannel XOver, need to be fed the same clock. The time difference induced by the signal manipulation (IIR,FIR) would be far greater than an eventual phase or frequency difference between clocks to the DACs?
So, maybe if you run all channels without any signal manipulation (whats the reason?), yes it could have an impact but when you insert your first filter or *delay* 8-o , this does not matter any more. Thats my view on this.
twest820 seem to answer on something else or maybe it was me not understanding the Q.
/
edit: my reasoning is based on that (really) good clocks are used.
So, maybe if you run all channels without any signal manipulation (whats the reason?), yes it could have an impact but when you insert your first filter or *delay* 8-o , this does not matter any more. Thats my view on this.
twest820 seem to answer on something else or maybe it was me not understanding the Q.
/
edit: my reasoning is based on that (really) good clocks are used.
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The most accurate crystals and oscillators readily available for audio clocks have an initial accuracy of 10ppm and a 10ppm aging tolerance. It's more likely 25 or 50ppm parts are used but let us assume the miniDSP and the DACs are all new and using 10ppm parts. This means the DSP clock and any given DAC clock will be within 20ppm of each other, which is a mismatch of 0.9 samples per second in redbook audio. So, if the DAC clock is running faster than the DSP is sourcing data it would have to make up a sample every 1.25 seconds. If the DAC is running slower, it would have to drop as sample.
This sample stuffing and dropping is basically what an ASRC does. PLLs solve the issue by locking an oscilator to the incoming clock frequency so that if the source is running at, say, 11.2897129MHz instead of the nominal 11.2896MHz 256Fs clock for redbook audio, the DAC runs 1.129Hz faster to match. If neither solution for crossing between the two clock domains is in place then somewhere inside the DAC the samples that are clocked into the DAC by the I2S SCK is clocked out by an MCLK running at a different rate. What specifically happens depends on how the registers are read and written. If you're lucky the worst that occurs is samples being lost or read twice but it's rather more likely bits will be garbled or parts of two samples will be combined into a new, incorrect sample.
Once data corruption occurs any phase behavior is irrelevant as there's no longer any signal to measure the phase of. In our example above it would take 90 milliseconds for two clocks to differ by one bit so, even if the clocks happened to start in the same phase (they won't) they'd be out of sync by the time the SigmaDSP part in the miniDSP has booted up and started sending data. If other problems with unmanaged clock domain translations such as latch up manage not occur then it's likely the DACs would play back corrupt data from the first sample to the last. Though, sure, there might be a couple correct samples in there.
This sample stuffing and dropping is basically what an ASRC does. PLLs solve the issue by locking an oscilator to the incoming clock frequency so that if the source is running at, say, 11.2897129MHz instead of the nominal 11.2896MHz 256Fs clock for redbook audio, the DAC runs 1.129Hz faster to match. If neither solution for crossing between the two clock domains is in place then somewhere inside the DAC the samples that are clocked into the DAC by the I2S SCK is clocked out by an MCLK running at a different rate. What specifically happens depends on how the registers are read and written. If you're lucky the worst that occurs is samples being lost or read twice but it's rather more likely bits will be garbled or parts of two samples will be combined into a new, incorrect sample.
Once data corruption occurs any phase behavior is irrelevant as there's no longer any signal to measure the phase of. In our example above it would take 90 milliseconds for two clocks to differ by one bit so, even if the clocks happened to start in the same phase (they won't) they'd be out of sync by the time the SigmaDSP part in the miniDSP has booted up and started sending data. If other problems with unmanaged clock domain translations such as latch up manage not occur then it's likely the DACs would play back corrupt data from the first sample to the last. Though, sure, there might be a couple correct samples in there.
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Thanks for the informed responses! Seems I have been too obsessed with the analogue side of this project and have not paid the digital side enough respect!
I will study the chip set clocking diagrams to see if they make any sense to me but I'm thinking there may well be phase anomalies but they would equate to the driver voice coils being offset by a few mm's i.e its an issue but a small one.
As far as filter delays go... the mini DSP allows for tweaking of this but the DAC clocking issue is random and cannot be compensated for.
Interested any further comments as well please
I will study the chip set clocking diagrams to see if they make any sense to me but I'm thinking there may well be phase anomalies but they would equate to the driver voice coils being offset by a few mm's i.e its an issue but a small one.
As far as filter delays go... the mini DSP allows for tweaking of this but the DAC clocking issue is random and cannot be compensated for.
Interested any further comments as well please
You hit the nail. Get good clocks. What do You prefer (in, say a 2-way system):
- LF stable, HF phase wanders.
- LF phase wanders, HF stable.
- Both LF and HF wanders.
- LF and HF stable, no relative wander (due to clocks)
....
Then the few mm can be fixed with delay function in XO.
Whats kind of output do the XO use? s/pdif... if yes; all DACs are synchronized via a PLL in the DACs to the XO and You are left with a jitter issue (maybe) and not with one of constant relative wonder between DACs. The deviation between the DACs will be up to the DAC PLL (assuming s/pdif) so they may drift apart but not constantly - they are pulled back by via the PLL to follow the XO.
Get good clocks
(I'm not sure minidsp is top notch here)/
If miniDSP documents their expansion header's pinout I've not found it, but presumably triplej is planning to tap the I2S lines on whatever one they have (2x4, 2x8, 8x8, ...) to drive triamped speakers. As the TAS5704 the miniAMP is built around has an MCLK input there's presumably an MCLK output from the miniDSP on the header. If so, this just needs to be fanned out to the DACs (if they're not ESS parts). Nothing random or uncompensatable about it; the clock distribution market is large, with a wide range of solutions at different price and performance points. Nominally it's just a matter of choosing one appropriate to the requirements, though I suspect a learning curve will be involved in this case.
twest820 Minidsp 2x4 i2s details: http://www.minidsp.com/images/documents/I2S technical note v2.pdf
I am not sure on the equiv document for the 2x8 or 8x8 since I've never gone looking.
I am not sure on the equiv document for the 2x8 or 8x8 since I've never gone looking.
Then the DACs will all lock to the whatever clock the nanoDIGI uses to clock the data out. From the block diagram I'd guess the nanoDIGI uses an ADAU1445 or similar and routes its input to the SigmaDSP's SPDIF reciever, in which case the DSP will be clocked off the crystal on the board since the SigmaDSP part's brickwall ASRC must be used in this configuration. You can get the details from a look at the board and the corresponding chip(s) datasheets.
@hochopeper: Thanks; the MCLK direction looks to be into the DSP rather than out of it. What I get for forgetting the ADAU1701 in the 2x4 doesn't have ASRCs on board.
@hochopeper: Thanks; the MCLK direction looks to be into the DSP rather than out of it. What I get for forgetting the ADAU1701 in the 2x4 doesn't have ASRCs on board.
Good news. Crisis averted. If I'm just dealing with "standard" jitter issues...I can live with that.
Thanks for the guidance.
How to synchronise several AD1865 DAC Nos SRPP
Hi guys
Good thread, am trying to understand how to connect 3 of these (excellent) ebay DACs after a MiniDSP nano digi 2x8 board that feeds SPDIF. Upfront I have a PC then waveIO board which I believe has quite a good clock. I am getting confused by the different stacks of clocks
Schematic there http://forums.melaudia.net/attachment.php?aid=2429
If I try to wrap up :
- the DAC board is using CS8414 which Will produce a clock signal from incoming SPDIF (from schematic I got M3 =0, M2 =M1= 1, M0 = 0 which in the 8414 datasheet means Format 6 out, L/R, 18 bits LSBJ)
- so every board Will generate its own clock SCK, which may not be excellent - rated 200 ps RMS in the datasheet
So, what are the good solutions and how difficult to implement ? I am obviously a newbie there
1- leave as is with different clocking, maybe the effect is not too bad
2- link AD1865 #2 and AD1865 #3 CLK to the clock of AD1865#1 (cut the original traces). i guess i have to do the same for SCK going to the latches ? Is there enough power for that mods ? What should I do with grounds ?
3- link AD1865 #1 to 3 to an external clock ? Which one is a good value for €?
4- link AD1865 #1 to 3 to an Wave IO clock ?
5- maybe the proper solution is still something else ...
Thanks
Jean-Louis
Hi guys
Good thread, am trying to understand how to connect 3 of these (excellent) ebay DACs after a MiniDSP nano digi 2x8 board that feeds SPDIF. Upfront I have a PC then waveIO board which I believe has quite a good clock. I am getting confused by the different stacks of clocks
Schematic there http://forums.melaudia.net/attachment.php?aid=2429
If I try to wrap up :
- the DAC board is using CS8414 which Will produce a clock signal from incoming SPDIF (from schematic I got M3 =0, M2 =M1= 1, M0 = 0 which in the 8414 datasheet means Format 6 out, L/R, 18 bits LSBJ)
- so every board Will generate its own clock SCK, which may not be excellent - rated 200 ps RMS in the datasheet
So, what are the good solutions and how difficult to implement ? I am obviously a newbie there
1- leave as is with different clocking, maybe the effect is not too bad
2- link AD1865 #2 and AD1865 #3 CLK to the clock of AD1865#1 (cut the original traces). i guess i have to do the same for SCK going to the latches ? Is there enough power for that mods ? What should I do with grounds ?
3- link AD1865 #1 to 3 to an external clock ? Which one is a good value for €?
4- link AD1865 #1 to 3 to an Wave IO clock ?
5- maybe the proper solution is still something else ...
Thanks
Jean-Louis
Any clocking expert
Hi all
Any idea on above ?
I have discovered in the meantime an alternative to MiniDSP nano digi : the very nice DSP Xover project http://www.diyaudio.com/forums/digital-line-level/215379-dsp-xover-project-part-2-a-34.html where same matter was discussed but did not came to definitive conclusion how to connect my DACs AD1865, Who are on master mode, to the DSP Xover which is too on master mode...
Kind regards
Jean-Louis
Hi all
Any idea on above ?
I have discovered in the meantime an alternative to MiniDSP nano digi : the very nice DSP Xover project http://www.diyaudio.com/forums/digital-line-level/215379-dsp-xover-project-part-2-a-34.html where same matter was discussed but did not came to definitive conclusion how to connect my DACs AD1865, Who are on master mode, to the DSP Xover which is too on master mode...
Kind regards
Jean-Louis
Hi Jean-Louis,
You have taken the clocking analysis further than I have. I was happy with the explanation that the various DAC's will simply synch of the incoming SPDIF. Is the clock of the nanodigi worthy? That im not sure.
At the end of the day I think i have bigger distortion issues elswhere in the active speaker design so learning more about those!
Regards
Triplej
You have taken the clocking analysis further than I have. I was happy with the explanation that the various DAC's will simply synch of the incoming SPDIF. Is the clock of the nanodigi worthy? That im not sure.
At the end of the day I think i have bigger distortion issues elswhere in the active speaker design so learning more about those!
Regards
Triplej
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