SPDIF receivers - internal architecture
 

I am curious - what exactly is a typical spdif receiver built around ? Is it a microcontroller ? Is it hardwired for all the logic and processing that goes on inside or is it software driven ?
Things like detecting the preamble and channel status bits and decoding the frames into the actual sample, and ofcourse the whole pll/clock recovery business.
And now receivers like WM880x incorporate a so called "buffer" to eliminate jitter down to 100hz. So on what platform are such things implemented ? Is it a highly customized hardware application (hardware building blocks like gates and flip flops tied together) or is it some sort of a processor handling everything by software ?
I know of "aftermarket" implementations using FPGA and XMOS and such but I asking about that $2-$5 chip you can buy from TI or CS or WM.

I'd guess its a purely digital hardware state machine plus a PLL which is digital in the case of the WM8805 and analog in the others. So 'yes' to your question about is it flip flops and gates - doing it in software would require more power and more silicon real-estate I reckon.

Doing it in hardware would also be quite an effort. Imagine the number of digital logic building block hardware combinations you would need to make to accomplish even a simple task as detect the preamble, then extract the 13th thru 27th bit, and then decode it to 16 bits from BMC. How would you go about doing that ?
I understand in 1980 processing power especially in miniature form was not available but today its a different story.

Its a job for a state machine compiler- you could do this with a CPLD I guess and there are high level languages for programming them, like Abel. That's a hardware description language - http://140.113.144.123/Creative/abel_ref.pdf

noticed the RD30 has its own software spdif receiver, says its even handles 187.4khz. Probably easier for the designer to start anew than figure out the silly WM8804.

Times they are a changing.