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Old 24th December 2012, 02:28 AM   #21
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Originally Posted by abraxalito View Post
The reason to reduce the supply is to keep the power supply noise low as noise is enemy no.1 to decent sound. The edge speeds reduce nicely at such a low supply voltage.

I doubt reducing the operating voltage of the glue logic will have much effect on the performance of the DAC since the logic is powered from an independent supply. A more appropriate measure would be to convert the 64-bit stereo frame to two 32-bit mono frames operating at half the bit clock rate. That will reduce the power draw and associated noise considerably. Easy to do with mono or dual-mono DACs like the AD1865.
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Old 24th December 2012, 02:32 AM   #22
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Well if you're talking about adding glue logic to reformat the data then it doesn't make sense to run the clock at 32fs to me. But its always a trade off between amount of logic (which itself draws power and generates noise) and optimizing the signals to the DAC.
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Old 24th December 2012, 02:49 PM   #23
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It seems to me that the difficulty in making these determinations is the lack of sufficiently accurate jitter measurement tools AFFORDABLE to the home hobbyist. I've become increasingly uncomfortable with simply applying circuit and layout techniques which, in theory, should reduce jitter. I would like to know what effect such techniques are actually having on jitter. If anyone knows of any such affordable tools, please share your knowledge. I currently have a decent 192ksps, 24-bit PC sound card from M-Audio with which I currently perform spectral analysis and FR plots. Perhaps, there is an inexpensive Windows based software tool available?
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Last edited by Ken Newton; 24th December 2012 at 02:55 PM.
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Old 24th December 2012, 06:21 PM   #24
marce is offline marce  United Kingdom
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Isolated power for the crystal/osc either with an LDO or minimum cap, ferrite, cap.
Place the crystal/osc as near as humanly possible to the clock input pin, the clock traces should be as short as possible. Simulate signal integrity using SIV software to check waveform and determine whether any termination is required. If driving more than one chip (or it has to travel any distance) use a clock ditribution ic, again check signal using SIV software taking layout into account and determine what if any termination is required. Thats what happens for realy critical stuff. Then some kit where you can get eye diagrams to check everything, It would be interesting to see what some clock mods do do to the signal...
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Old 14th February 2013, 01:11 AM   #25
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Im thinking of using Mic5207 regulators in adaptors instead of Salas regs, in order to keep the size of construction more compact. I was looking the datasheet (http://www.micrel.com/_PDF/mic5207.pdf) and saw this :

"Dual-supply operation.
When used in dual-supply systems where the regulator load is returned to a negative supply, the output voltage must be diode clamped to ground."

Is the orientation of the diodes correct in the attached picture?
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File Type: jpg diode-orientation.jpg (33.9 KB, 274 views)
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Old 28th February 2013, 12:30 AM   #26
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Finished construction of the CS8416 and AD1865 Iout boards today.
First impression is really positive.
I am starting to see why people say multibit dacs are better.
The music is more engaging, sound is easier to listen and full of detail.

Next upgrade will include changing the rectifiers to soft recovery types and low noise regs.

The only downside is the relatively low output volume because of the passive i/v (200r Susumu RG). Im feeding the signal to a MyRef RevC through a 10k stepped attenuator

Would an opamp gain stage after passive i/v be a bad idea? ( I have some LT1361 and opa627 laying around )
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Old 28th February 2013, 12:49 AM   #27
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Opamps tend not to like the high levels of RF coming out of DACs, I recommend passive (LC) filtering before the opamp - OPA627 is one of the better ones at dealing with RF. Better still though an AFA like AD830, this one is highly RF resistant and sounded great when fed with TDA1545.
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Old 28th February 2013, 01:04 AM   #28
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Quote:
Originally Posted by skouliki View Post
Finished construction of the CS8416 and AD1865 Iout boards today.
First impression is really positive.
I am starting to see why people say multibit dacs are better.
The music is more engaging, sound is easier to listen and full of detail.

Next upgrade will include changing the rectifiers to soft recovery types and low noise regs.

The only downside is the relatively low output volume because of the passive i/v (200r Susumu RG). Im feeding the signal to a MyRef RevC through a 10k stepped attenuator

Would an opamp gain stage after passive i/v be a bad idea? ( I have some LT1361 and opa627 laying around )
You might well consider adding an op-amp voltage gain stgae after that 10K attenuator. That would allow you to use a much lower passive I/V resistor, thus provoking less distortion at the AD1865's outputs, while both increasing the output signal level and lowering it's output impedance. I find that the sound becomes more focused, more solid, as the passive I/V resistor value is lowered.
Compensate for the reduced signal amplitude via the op-amp gain setting. In addition, be sure to low-pass filter the signal somewhere above 20KHz and prior to the op-amp inputs.
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Old 28th February 2013, 09:13 PM   #29
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Thanks you guys for your suggestions.
I'll try to do both and see what i like best.

What value for i/V resistor do you recommend? Is 50R low enough or can i use even lower values?

About using an RC filter on the opamp inputs (excuse my cluelessness! ): Inserting a capacitor to ground after the I/V resistor forms an RC filter or not?
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Old 1st March 2013, 12:26 AM   #30
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50R should be fine. Even so, you could experiment with lower values while compensating via the opamp gain setting. Use your ears to judge where the best tradeoff occurs. Don't sweat this too much, if you don't feel you hear an improvement then leave well enough alone.

Yes, a capacitor to ground (meaning, in parallel with the I/V resistor), while better than nothing, will form too shallow a roll off slope to provide significant digital image rejection.
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Last edited by Ken Newton; 1st March 2013 at 12:30 AM.
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