AD1865 schematic

[regal]

With this design there's going to be inevitably a lot of jitter, the cs8416 spdif plus the glue logic...


Did you see the iancanda board at the top of the page, its ideal for AD1865 because it does the delay/conversion and synchs the clocks for you with the lowest jitter possible also would allow the option to try other R2R chips in NOS mode with protoboards like the one abraxilito posted (I just ordered 4 of those they look great.)

[skouliki]

Yes FIFO would be great, but i cannot really afford it right now.

[abraxalito]

Not really worth worrying too much about jitter - I don't find it a problem in terms of the subjective SQ when running multibit DACs. Definitely though its an issue on S-D DACs. Rather worry about reducing noise modulation, that's the biggest detractor from SQ.

[regal]

Originally Posted by abraxalito

Not really worth worrying too much about jitter - I don't find it a problem in terms of the subjective SQ when running multibit DACs. Definitely though its an issue on S-D DACs. Rather worry about reducing noise modulation, that's the biggest detractor from SQ.

What do you think about this schematic, is it worth adding the extra noise to align the channels ?

[abraxalito]

You mean is it worth adding a long shift reg? I doubt I'd bother - the delay of one sample I don't think is audible. I would though on that circuit prefer to run the HC logic at 2.5V rather than 5V. If you added an HEF4517 to do the shifting, I doubt that would add much noise though, being 4000 series, the slowest known CMOS

[regal]

Originally Posted by abraxalito

You mean is it worth adding a long shift reg? I doubt I'd bother - the delay of one sample I don't think is audible. I would though on that circuit prefer to run the HC logic at 2.5V rather than 5V. If you added an HEF4517 to do the shifting, I doubt that would add much noise though, being 4000 series, the slowest known CMOS

Yes that's what I meant, I can hear the delay with headphones. One thing I'm not sure of in these schematics is he calls for 24 bit I2s, but most I2S output USB stuff use a 256x clock. I think its a gotcha if anyone is planning on using these with a usb-i2s device.

[skouliki]

Originally Posted by abraxalito

You mean is it worth adding a long shift reg? I doubt I'd bother - the delay of one sample I don't think is audible. I would though on that circuit prefer to run the HC logic at 2.5V rather than 5V. If you added an HEF4517 to do the shifting, I doubt that would add much noise though, being 4000 series, the slowest known CMOS

So the optimal voltage for 74HCT164 in that circuit is 2.5v. Can you explain why? Sorry, im kinda clueless

[Tam Lin]

Originally Posted by abraxalito

You mean is it worth adding a long shift reg? I doubt I'd bother - the delay of one sample I don't think is audible. I would though on that circuit prefer to run the HC logic at 2.5V rather than 5V. If you added an HEF4517 to do the shifting, I doubt that would add much noise though, being 4000 series, the slowest known CMOS [IMG]file:///C:/Users/jb/AppData/Local/Temp/msohtmlclip1/01/clip_image001.gif[/IMG]

A design goal of Pavouk's DAC is 192K operation. The HEF4517 is too slow, as Pavouk found out. At 2.5V the HC164 is not fast enough, either. Besides, shifting the data will have little impact on sample clock jitter. Even though BCK is driving seven loads, it is of little consequence. With the AD1865, the low-going latch edge updates the respective DAC output. Most other DACs update on a rising BCK edge.

[regal]

Originally Posted by Tam Lin

Even though BCK is driving seven loads, it is of little consequence. With the AD1865, the low-going latch edge updates the respective DAC output. Most other DACs update on a rising BCK edge.

That's interesting to know could this be one reason why the AD1865 is more popular than the seemingly identical the PCM56k/PCM58k

[abraxalito]

Originally Posted by skouliki

So the optimal voltage for 74HCT164 in that circuit is 2.5v. Can you explain why? Sorry, im kinda clueless

Its not HCT, that wouldn't work at 2.5V, its HC. As Tam Lin has pointed out that 192k operation was desired by the originator, then he might indeed be correct about the speed of the HC164 not being sufficient at 2.5V; however I'd not recommend running a DAC at 192k. Its throwing away some of the advantage of using the AD1865 to run it so fast and there's no audio benefit, only detraction of running at such a high SR.

The reason to reduce the supply is to keep the power supply noise low as noise is enemy no.1 to decent sound. The edge speeds reduce nicely at such a low supply voltage.