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Old 21st November 2012, 09:29 AM   #31
marce is offline marce  United Kingdom
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I2S is a flavour of the serial peripheral interfaces that are becoming more common for inter device communication, very similar to I2C. When the IBIS models of the various drives are compared they are basically the same, some Ti codecs have both interfaces.
All of these should be laid out in daisy chain fashion where more than one device is used and as a bus, i.e. all signals together. We see more problems with these types of buses than a lot of others as quite often they are routed as separate signals all over the place.
Transmission line rules apply to these and we will sometimes simulate them using the signal integrity verification software. Numerous reasons why, one of the main being, if you look at the IBIS data for a lot of serial drivers they are quite low impedance with quite a strong current output, so often the signals will have quite a few reflections. Using the simulation software allows us to calculate the values of any termination required to match the PCB characteristic impedance.
Standard PCB impedances for digital signals are usually between 50-100Ohm, depending on thickness of copper, trace width and distance from return signal plane. You can use this:
Saturn PCB Design - PCB Via Current | PCB Trace Width | Differential Pair Calculator | PCB Impedance
to do some rough and ready impedance calculations. For the simulation software there is a full 3D field solver that does a much more accurate job, though you do have to detail your PCB stack up with thickness of all layers and the materials used for the pre-pregs and laminates (we have a data base of all the common current laminates available that we use).

An example of a 12 layer stack up attached below. Only about 35% of the designs I do are actually controlled impedance boards, his is due to the increased manufacturing costs mainly, as you are adding 15-25% to the cost of each PCB, depending whether you want the value controlled to 10% standard or 5%. The rest, are standard boards, where your impedances will be within 20-25% of your desired impedances. For a true controlled impedance PCB the manufacturer has to do a test coupon for every panel and measure the impedance of every test coupon before the boards can be released. The main breakpoint for companies to consider both controlled impedance designs and simulation at the moment is when they start to use DDR memory interfaces (even then a lot donít, due to costs). But with the ever increasing rise time of todays devices, signal integrity is becoming more critical for even the most basic circuits. As said we are seeing more request for simulation on common busses that arenít considered as high speed but are critical, these being JTAG clocks and sometimes the full JTAG bus, SPI in its many guises and clocks in general, even down to 12MHz clocks.
Most people look at the clock frequencies on a design and use these to determine whether a design is high speed, WRONG. As Dr Howard Johnson points out in his literature and seminars, high speed is determined by the rise time of the signals on your board, and t is the Knee frequency that determines the spectral content you have to cater for.
Instead of me rabbiting on about PCB impedance here is a link to Polar Instruments site:
PCB signal integrity and controlled impedance Ė PCB troubleshooting
When we do controlled impedance designs we work closely with the manufacturer, who use the polar tools to help work out our required PCB stack up, the laminates to use and the thickness of these laminates. We then enter this information into the PCB design layer stack up so that the simulation software is working on the correct data.
Again to get a full understanding of the issues, read and study any information (and books) from the likes of:
Dr Eric Bogatin: beTheSignal.com
Dr Howard Johnson: Signal Consulting, Inc. - Dr. Howard Johnson
Henry Ott: home page
Lee Richley: Right the First Time, A Practical Handbook on High-Speed PCB and System Design is now available
And this book is a good read with numerous stack up examples:
Charles Pfeil: Leading Successful BGA Design Solutions - Mentor Graphics
you can download a free PDF version.
Its only a brief look at the fun all this is, to put it into context of system etc, I have over £50K worth of software at my disposal, with the basic schematic and PCB packages, with constraints manager, high speed routing tools, simulation software for both signal integrity and power deliver system (both ac and dc simulations), EMC adviser, thermal and a full 3D CAD system (Inventor) for making sure everything fits in the box, and very liitle sleep!

Last point, if we dont use transmission line theory what do we use!I,m puzzled on that one as in over 25 years of playing about with high speed PCb design (VME, ecl etc in the 80s) I've always used transmission linetheory and calculators etc.
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Old 21st November 2012, 03:46 PM   #32
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Quote:
Originally Posted by qusp View Post
all the PCBs i'm using are using a controlled impedance
What are the chosen impedances? While I2S doesn't specify a value a de facto standard would be helpful for letting DIY modules work better together. I've defaulted to 120 ohms as that's natural for low cost two layer PCBs, routes decently with 0.5mm pitch packages, and not too difficult to find in ribbon cable.
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Old 21st November 2012, 03:58 PM   #33
marce is offline marce  United Kingdom
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Matching the drive to the PCB impedance is what is critical for ultimate signal integrity., these serial buses are designed to work on a variety of PCBs with differing impedances so generally you have a low output drive impedance and a higher input impedance
There is a lot of documentation regarding the i2c bus that is relevant to i2s, including information for taking the uses over CAT 5 twisted pair cable.
Two layer with digital is OK, if you can get a good contigous ground plane on the bottom layer.
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Old 21st November 2012, 05:24 PM   #34
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Easily handled with some 0603 source terminations (or smaller, if one feels like itty bitty soldering). 100 ohm for compatibility with Ethernet hardware is the main alternative to 120 ohm, hence my question to qusp.

Last edited by twest820; 21st November 2012 at 05:29 PM.
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Old 21st November 2012, 05:45 PM   #35
marce is offline marce  United Kingdom
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Ethernets 100 Ohms is for differential pair, single ended signals are 50 Ohm, when we do a controlled impedance board these are the figures we require (for the majority of signals), the high speed routing engine will change the track width as you change layers to keep the impedance constant.
As said a lot of these devices are desihgned to work under all conditions, and one of the beauties of digital it does work well on most designs, we very rarely see problems with most standard digital, its as I said earlier when DDR, gigabit ethernet and the LVDS serial interfaces that clock along at silly speeds come along we see problems where simulation and checking the layout has not been done (often for cost, cheep PC motherboards)
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Old 21st November 2012, 06:30 PM   #36
macboy is offline macboy  Canada
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Quote:
Originally Posted by marce View Post
Matching the drive to the PCB impedance is what is critical for ultimate signal integrity., these serial buses are designed to work on a variety of PCBs with differing impedances so generally you have a low output drive impedance and a higher input impedance
There is a lot of documentation regarding the i2c bus that is relevant to i2s, including information for taking the uses over CAT 5 twisted pair cable.
Two layer with digital is OK, if you can get a good contigous ground plane on the bottom layer.
I can hardly believe that you are lumping I2S together with I2C, they are completely different! I2S is point-to-point, and I2C is a multi-device bus. I2C uses open-collector drivers and pull-up resistors and has a signalling rate of 100 kHz, 400 kHz or a max of 3.4 MHz. The pull-ups are always well over 1 kΩ and sometimes much higher, so any talk of controlled impedance for I2C is almost humorous. I2S has completely different electrical characteristics, and as far as I can tell, any documentation or knowledge concerning implenting I2C is not applicable to I2S. The only exception I can see is when referring to specialized long-range I2C transmitters/receivers, which due to the necessity of long distance transmission, use transmission line theory complete with controlled impedance drivers, cables, and terminations. All of that is completely foreign to 'normal' I2C.

With that said, you obviously know what you are talking about w.r.t. controlled impedance PCB design. I think that the big unanswered (and remarkably, unasked!) question here is: What is the characteristic impedance of the I2S signal traces on the two PCBs that are being connected together?. That, of course, will determine what the characteristic impedance of the interconnect cabling should be. If these boards are DIY or designed by non-pros, then they may not have been designed to any specific impedance at all! It should be possible to calculate the impedance using the geometries of the PCBs (trace width, distance to ground, etc.) or measured by TDR techniques if the traces are long enough and a high speed scope is available.

Last edited by macboy; 21st November 2012 at 06:33 PM.
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Old 21st November 2012, 07:02 PM   #37
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Originally Posted by marce View Post
Ethernets 100 Ohms is for differential pair, single ended signals are 50 Ohm
I think 50 ohms is probably a non-starter---that's a ~93 mil trace for two layer FR4 62 mil boards, which is painfully fat. If one's doing a long haul it would make sense to put down LVDS PHYs but I2S directly over Ethernet patch cables has its attractions for sort haul.

Quote:
Originally Posted by macboy View Post
I think that the big unanswered (and remarkably, unasked!) question here is: What is the characteristic impedance of the I2S signal traces on the two PCBs that are being connected together?
Agree. Hence the suggestion of establishing a de facto standard.

Quote:
Originally Posted by marce View Post
we see problems where simulation and checking the layout has not been done (often for cost, cheep PC motherboards)
Yeah, there's a reason Intel does the sims, publishes layout guidelines, and provides reference designs. But sometimes copying them is too hard. (Though, in fairness, I've never checked to see if other chipset vendors do the same, though I'd expect they'd have to in order to be competitive...)

Last edited by twest820; 21st November 2012 at 07:07 PM.
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Old 21st November 2012, 07:11 PM   #38
marce is offline marce  United Kingdom
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My bad, I though i2s was a derivitive of i2c. We see i2c on nearly every job these days, and recently it was used as the go between between several Ti 320 series codecs, the multipoint must be why that was used and not the i2s pins on the devices.
The saturn toolkit will give a quick impedance calc based on basic geomatry, use that a lot for determining basic track widths when we are not gonna use the high speed stuff.
For normal baords the width tolerance is usually +/-10%.
Again I was mistaken about the similarities between the two buses, I will study the I2s spec in more detail.
In regards to your question, what happens if the boards have differing impedances? if the same then there is no problem, but say connecting a DIY board to a proffesionaly manufactured one there could be quite a difference.
Cheers, like lots here I am still learning and stand corrected
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Old 21st November 2012, 07:29 PM   #39
marce is offline marce  United Kingdom
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Most commercial digital baords are a minimum of four layers, when you have a DDR interfaces usually six is the minimum and often 8-14 layers are empoloyed as well as multiple power pairs, the proliferation of BGA devices require more layers just to get the traces out of the device. Though as youve pointed out for a two layer board the width is silly, a 12 mil (0.3mm) trace give about 120 ohm as you suggested, interesting though if you do a 4 layer board with three equal cores (roughly 0.5mm each), my calculater give a trace width of 3mil to achieve the same impedance!
Most devices now have layout guides, some of Xylinz's are huge, though the Intel spec for DDR interface is not a light read. Where possible we follow the guidlines given ro use a reference design for some guidance, no point re-inventing the wheel.
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Old 21st November 2012, 08:01 PM   #40
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Yeah, there's probably not a good way to choose an impedance value that works for both two and four layers on low cost boards, especially if the four layer is EMI optimized and has close outer spacings in the SPGS stackup.

However, I've yet to see a four layer board used in a dedicated audio application; every DIY candidate I've taken apart or looked at closely on the 'net has been two layer. That's not to say there aren't 4+ layer boards out there carrying audio---there's of course a plethora of PCs, phones, and so on---just that it seems a de facto impedance standard aimed at two layer would cover the majority of cases where a DIYer would want to integrate different modules using I2S.

Last edited by twest820; 21st November 2012 at 08:06 PM.
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