Digital, but not by the numbers

[erin]

Originally Posted by fas42

At a simplistic level the problems of delta sigma appear to lie in 2 key areas: they need long conditioning times, of the order of hours before properly coming on song, when started from cold; and, they are very susceptible to interference.

This has been my experience, with units some years old. The latest offerings may be better, perhaps ...

Frank

I do listen to equipment for a couple of hours before making a judgement.
My experience is that the Burr Brown PCM58 and PCM1702 both need about 30 minutes to sound good.

The TDA1541 sounds very good straight away, but will improve subtly over a few hours.

[PHEONIX]

Hello qusp,

Can I ask what the difference in sound quality is when you run the sabre in synchronous mode.

I sent you an email on what hardward etc was required to do this with the sabre dac.

[marce]

Qusp
Is this problem with the ES9018 prevelant on every design incorporating this chip? Do we know the change in temerature etc.
It sounds quite an interesting phenonema, and one (involving integrated circuits)that I haven't heard about for many many years, I am going back to mid/late 80's and work that the firm I was with then did in conjuction with Daresbury.
Most circuitry will if designed properly reach its operating temperature within a few to tens of minutes and then be stable (depending on ambient temp) but as this is commercial the temerature difference between homes isn't that much as we humans like to live within a nice comfy range of temps.

[qusp]

it may not be temp at all, its just using the term 'warm up' is habit. I live in QLD Australia, it doesnt usually have to warm up haha. I havent tried actively heating it. there are lots of factors that seem to contribute, but it seems tied to the grounding most of all. it may just take a little while for the loop to settle down, since jitter at these levels is a pretty long term/low frequency effect..

if you leave it on the default, as many commercial dacs will, its not an issue unless youve done something silly with your i2s connections, or have a VERY high jitter source and bad system grounding. Some commercial dacs do indeed have the problem. its only really when you manually set/force the DPLL bandwidth to the lower settings (best jitter rejection). its worst if you have a direct ground path to the dac from outside, like with a non-isolated USB->i2s (single ended), or with an MCU/i2c connection and ripple on ground gets into the system.

glt has done extensive testing and recorded the results



I repeat, the issue is with US DIYERs or manufacturers pushing the boundaries with DPLL bandwidth settings, use the default 'best' setting and it doesnt happen.

my best results when using lowest DPLL BW have been gained by using Ian's fifo and grounding the fifo clock power supply and ground on the same star point as the onboard clock used to with a thick wire

mainly i'm using synchronous clocking now though

Phoenix, I prefer Synchronous mode, but its more different than better than a very well done async mode build. I'm sorry I dont really do describing sound quality of such things when you and I have different ears and I can guarantee different gear/probably different taste and different music

unless you are going to do it well with a very low jitter source clock and proper interconnections I think you are better off staying with async

[marce]

I wonder if its PSU start up then, or supplies settling.
We did a job as I said back in the dim and different past, and using commercial chips we had similar problems, we solved it by bying military grade ADC's and DAC's (they were available and expensive in those days), lovely ceramic package with gold plated caps etc. Ended up with tubes of the things, cos no one else wanted them. Threw them away about 3/4 years ago when we moved, only to find out later they had a decent scrap value because of the gold...SOB!

[qusp]

I think its probably more of a case of Dustin pushing the boundaries with the DPLL BW settings he made available. when he designed the 9018 coming from the 9008, he made the default DPLL 128x narrower and also allowed manual setting of even more extreme narrow BW.

it could indeed have something to do with the voltage the clock swings around and the voltage the digital core logic swings around settling into equilibrium, made worse if the i2s BCK driver/buffer is external on another PCB and using another ground/voltage again. which was part of my reasoning for connecting the grounds from the single point with thick wire.

if you use the spdif inputs you dont get it either, because their 'lowest' is equal to 'best' with i2s.

its exacerbated by the fact this dac runs at 1.5MHz internally and we are all pushing the BW down and pushing up the sample-rates.

bitch about the gold, yeah even with copper these days you almost need to think about throwing things away.

[PHEONIX]

Originally Posted by qusp

it may not be temp at all, its just using the term 'warm up' is habit. I live in QLD Australia, it doesnt usually have to warm up haha. I havent tried actively heating it. there are lots of factors that seem to contribute, but it seems tied to the grounding most of all. it may just take a little while for the loop to settle down, since jitter at these levels is a pretty long term/low frequency effect..

if you leave it on the default, as many commercial dacs will, its not an issue unless youve done something silly with your i2s connections, or have a VERY high jitter source and bad system grounding. Some commercial dacs do indeed have the problem. its only really when you manually set/force the DPLL bandwidth to the lower settings (best jitter rejection). its worst if you have a direct ground path to the dac from outside, like with a non-isolated USB->i2s (single ended), or with an MCU/i2c connection and ripple on ground gets into the system.

glt has done extensive testing and recorded the results



I repeat, the issue is with US DIYERs or manufacturers pushing the boundaries with DPLL bandwidth settings, use the default 'best' setting and it doesnt happen.

my best results when using lowest DPLL BW have been gained by using Ian's fifo and grounding the fifo clock power supply and ground on the same star point as the onboard clock used to with a thick wire

mainly i'm using synchronous clocking now though

Phoenix, I prefer Synchronous mode, but its more different than better than a very well done async mode build. I'm sorry I dont really do describing sound quality of such things when you and I have different ears and I can guarantee different gear/probably different taste and different music

unless you are going to do it well with a very low jitter source clock and proper interconnections I think you are better off staying with async

Hello qusp,

Its my intention to use a low jitter clock and to do it well.

[fas42]

Just picked on another forum the latest in a discussion thread, which essentially bashes Redbook, against 128xDSD. This is from my POV, a nonsense, it's all about the quality of the playback electronics, that's determining the quality of the heard sound ...

I would like do an experiment of taking a highest quality, direct to 128xDSD recording, and then using the best software around downsample that to RB, then resample that 16/44.1 back up to 128xDSD. Do this exercise 100 times, so we're talking about 100 generations of resampling. Take the last generation copy of the DSD, and then see how many people can differentiate that from the original DSD ...

Why I say this is that I've done a number of experiments of upsampling nominally poor, low bit rate recordings, and every time this markedly improves the perceived quality, on a very ordinary playback setup. This is not because something has been "added" to the sound, but because less high speed processing has to be done to "digest" the digital info on playback, IMO ...

Frank

[Julf]

Originally Posted by fas42

I would like do an experiment of taking a highest quality, direct to 128xDSD recording, and then using the best software around downsample that to RB, then resample that 16/44.1 back up to 128xDSD. Do this exercise 100 times, so we're talking about 100 generations of resampling. Take the last generation copy of the DSD, and then see how many people can differentiate that from the original DSD ...

Well, as just one data point, something like a year ago I did run a blind listening test on another forum with a number of different versions of the same track - resampled at different sample rates, truncated from 24 to 16 bits, and one version even encoded using (high bit rate) mp3. The only consistent result was that the one version that had been amplified by 1 dB was the clear winner - the rest was practically random.

[erin]

Listener fatigue is the unknown factor, in listening tests.
This is why I prefer AB (two points of comparison) tests rather than ABCDEFG tests. Anyone can become muddled when listening to too many tracks, or equipment. But it is usually easy to declare a preference when comparing only one thing to another.