LPC3130 for asynchronous USB to I2S

[jonsmirl]

Nobody seems to have considered using the NXP LPC3130 (or LPC3131) as an Asynchronous USB to I2S converter. It is $3.89 Q1 at Avnet.

• 96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM

• High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY, 480Mb

• It is meant for a MP3 player so it can synthesize audio clocks (44.1, 48K multiples)

• You can dynamically download the software for it over the USB line. It boots in DFU mode.

• Available open source libraries implementing USB support

• Two dedicated I2S channels.

I think you could make a lot more IS2 channels by using the static memory interface. This interface has DMA capability and a 16b bus. The DMA is triggered from an external input. You could wire the audio clock output from an I2S channel into the external DMA trigger input.

Inside the CPU use software to serialize 15 channels of audio data and a word clock. Now when the audio clock triggers the SRAM DMA, clock out 15 channels of I2S and the word clock.

External devices should see this as 15 channels of I2S. Reverse the procedure for input.

96KB should be enough for the program an a good sized FIFO. If not use the LPC3131 and get 192KB of RAM.

[abraxalito]

Not a very DIY-friendly package that TFBGA180. But a great part for the price for sure.

[jonsmirl]

We can solder this chip in our lab, but it is a pain. For any significant quantity we have an assembly house solder.

Olimex makes a fairly cheap dev board for the chip. It has a lot of extra stuff on it. US disti

I suspect a USB to IS2 board can be made for under $20 using this chip. If someone gets this working I'll buy ten.

BTW, I've seen this chip go for $2.25 in huge quantity.

[abraxalito]

I remain skeptical of your use of DMA to bit-bang the 15 channels of output. - it would require bit-twiddling by the CPU which I reckon will be very cycle-intensive. Besides the SDR Widget guys already have an Open Source async solution, I think they were using an Atmel SoC though which is bound to be a bit more expensive than the NXP.

[jonsmirl]

It is a 180Mhz ARM9 core that would be dedicated to bit banging. USB arrives via DMA. At 96Khz that's 125 instructions per bit. For another $1 you can get a 270Mhz version which gives you 187 instructions per bit.

The 96K on-chip memory is SRAM so there are no refresh delays. There will be some interference from DMA. This is also a 32b CPU with lots of registers.

Based on these estimates it doesn't look hopeless.

[jonsmirl]

LPC3130 vs AT32UC3A3256 used in SDR widget

• $3.89 vs $12.47 - Q1
• 180Mhz vs 66Mhz
• 96KB RAM vs 128KB RAM
• can make audio clocks vs needs external oscilator
• download firmware from host vs 256KB flash
• 180-TFBGA vs 144-TFBGA

[twest820]

Hmm, if you're going to the trouble of coding up an asynchronous USB Audio Deivce Class 2.0 implementation for ARM why not target the LPC4300? Granted, the 4300 parts are a little more expensive but the clock rate is comparable, they're available in LQFPs, and the bit shuffling can be offloaded to the M0 and SGPIO.

[abraxalito]

Somewhat ironically the M0 isn't blessed with the very instruction (rotate with extend) that would make bit shuffling viable...

[mhelin]

Originally Posted by twest820

Hmm, if you're going to the trouble of coding up an asynchronous USB Audio Deivce Class 2.0 implementation for ARM why not target the LPC4300? Granted, the 4300 parts are a little more expensive but the clock rate is comparable, they're available in LQFPs, and the bit shuffling can be offloaded to the M0 and SGPIO.

I think the 4300 LQFP's ( LPC4320FBD144) aren't available yet. Also they don't have internal flash, and the second I2S port pins are mostly shared with the SPIFI pins which are used for interfacing the external flash. Anyway, there's the NGX LPC4330-Xplorer board with the (not so good) UDA1380 codec which you can use for development until you can design your own one with the LQFP part.

[jonsmirl]

There are two ways to use the LPC3130, bare metal or add a $1 SDRAM chip. Bare metal is cheaper and more efficient. NXP has basic support libraries for bare metal USB and I2S. No audio class 2 though.

The other approach is to run Linux on it using the SDRAM chip. Linux already has audio class 2 and I2S support.

The two on-chip I2S channels can do 96/24 per the manual. I suspect they can also do 192/24 but can't provide a 256 fs clock at 192/24. 64 fs should work.

I don't have a need for more than two I2S. The bit twiddling appeared to be possible so I just mentioned it.