Nobody seems to have considered using the NXP LPC3130 (or LPC3131) as an Asynchronous USB to I2S converter. It is $3.89 Q1 at Avnet.
Inside the CPU use software to serialize 15 channels of audio data and a word clock. Now when the audio clock triggers the SRAM DMA, clock out 15 channels of I2S and the word clock.
External devices should see this as 15 channels of I2S. Reverse the procedure for input.
96KB should be enough for the program an a good sized FIFO. If not use the LPC3131 and get 192KB of RAM.
96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM
High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY, 480Mb
It is meant for a MP3 player so it can synthesize audio clocks (44.1, 48K multiples)
You can dynamically download the software for it over the USB line. It boots in DFU mode.
Available open source libraries implementing USB support
Two dedicated I2S channels.
Inside the CPU use software to serialize 15 channels of audio data and a word clock. Now when the audio clock triggers the SRAM DMA, clock out 15 channels of I2S and the word clock.
External devices should see this as 15 channels of I2S. Reverse the procedure for input.
96KB should be enough for the program an a good sized FIFO. If not use the LPC3131 and get 192KB of RAM.
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We can solder this chip in our lab, but it is a pain. For any significant quantity we have an assembly house solder.
Olimex makes a fairly cheap dev board for the chip. It has a lot of extra stuff on it. US disti
I suspect a USB to IS2 board can be made for under $20 using this chip. If someone gets this working I'll buy ten.
BTW, I've seen this chip go for $2.25 in huge quantity.
Olimex makes a fairly cheap dev board for the chip. It has a lot of extra stuff on it. US disti
I suspect a USB to IS2 board can be made for under $20 using this chip. If someone gets this working I'll buy ten.
BTW, I've seen this chip go for $2.25 in huge quantity.
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I remain skeptical of your use of DMA to bit-bang the 15 channels of output. - it would require bit-twiddling by the CPU which I reckon will be very cycle-intensive. Besides the SDR Widget guys already have an Open Source async solution, I think they were using an Atmel SoC though which is bound to be a bit more expensive than the NXP.
It is a 180Mhz ARM9 core that would be dedicated to bit banging. USB arrives via DMA. At 96Khz that's 125 instructions per bit. For another $1 you can get a 270Mhz version which gives you 187 instructions per bit.
The 96K on-chip memory is SRAM so there are no refresh delays. There will be some interference from DMA. This is also a 32b CPU with lots of registers.
Based on these estimates it doesn't look hopeless.
The 96K on-chip memory is SRAM so there are no refresh delays. There will be some interference from DMA. This is also a 32b CPU with lots of registers.
Based on these estimates it doesn't look hopeless.
Hmm, if you're going to the trouble of coding up an asynchronous USB Audio Deivce Class 2.0 implementation for ARM why not target the LPC4300? Granted, the 4300 parts are a little more expensive but the clock rate is comparable, they're available in LQFPs, and the bit shuffling can be offloaded to the M0 and SGPIO.
I think the 4300 LQFP's ( LPC4320FBD144) aren't available yet. Also they don't have internal flash, and the second I2S port pins are mostly shared with the SPIFI pins which are used for interfacing the external flash. Anyway, there's the NGX LPC4330-Xplorer board with the (not so good) UDA1380 codec which you can use for development until you can design your own one with the LQFP part.
There are two ways to use the LPC3130, bare metal or add a $1 SDRAM chip. Bare metal is cheaper and more efficient. NXP has basic support libraries for bare metal USB and I2S. No audio class 2 though.
The other approach is to run Linux on it using the SDRAM chip. Linux already has audio class 2 and I2S support.
The two on-chip I2S channels can do 96/24 per the manual. I suspect they can also do 192/24 but can't provide a 256 fs clock at 192/24. 64 fs should work.
I don't have a need for more than two I2S. The bit twiddling appeared to be possible so I just mentioned it.
The other approach is to run Linux on it using the SDRAM chip. Linux already has audio class 2 and I2S support.
The two on-chip I2S channels can do 96/24 per the manual. I suspect they can also do 192/24 but can't provide a 256 fs clock at 192/24. 64 fs should work.
I don't have a need for more than two I2S. The bit twiddling appeared to be possible so I just mentioned it.
Interesting idea. Which distro did you have in mind? I was going to mention the 4300 boot ROM supports DFU but Abraxilito beat me to it.
Try Digikey; started stocking 'em back on the A2 stepping. Agree the odds of pin assignment conflicts are good---it's not the biggest package and most pins have half a dozen different functions---but if you can scrape together three SGPIO slices someplace then it's pretty easy to roll an I2S.
I don't know the LPC3130 off the top of my head but the LPC4300 I2S peripherals are duplex and include clock lines. So if one just needs a stereo USB <-> I2S then the I2S0 peripheral would be sufficient. I would guess that's a standard block NXP puts down and that the 3130 has it as well. But while Jon mentions he doesn't need more than two I2S I don't know which way they're going.
Why is a shift needed when copying 16 or 24 bit samples from USB to I2S?Somewhat ironically the M0 isn't blessed with the very instruction (rotate with extend) that would make bit shuffling viable...
If one's doing DSP on them along the way then, yeah, probably ASR/ASL are needed to get Q0.whatever on [ -0.25, 0.25 ). But probably the M4 is doing the DSP.
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Its not the copying the samples from USB to I2S that needs that instruction. jonsmirl originally was suggesting 15 parallel bit-banged streams of I2S using DMA, rearranging the bits in software first. That's what seems to me to need the extend bit but I'll be very happy if somebody explains a more efficient way to handle it
I usually start with OpenWRT and then remove things. A 2MB image for doing this is not impossible. 4MB is easy and you'd get a web server too. Downloading 2MB over a 480Mb link is fast.
I don't know the LPC3130 off the top of my head but the LPC4300 I2S peripherals are duplex and include clock lines---I would guess that's the a standard block NXP puts down. So if one just needs a stereo USB <-> I2S then the I2S0 peripheral would be sufficient. Jon mentions he doesn't need more than two I2S but I don't know which way they're going.
I want two output lines for bi-amping a pair of speakers.
Why is a shift needed when copying 16 or 24 bit samples from USB to I2S?
The LPC3130 has a parallel SRAM interface that could be used to bitbang upto 15 I2S channels. That's where the shift discussion came from. I don't need 15 I2S, just mentioned it as a possibility.
Though only USB0, the errata (link:http://www.nxp.com/documents/errata_sheet/ES_LPC43X0_A.pdf) says USB1 cannot be used for booting.
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I imagine you'd want the 3130 for the MMU then. uClinux does support the 4350 but I don't think it implements USB audio (in fact, I'm not sure there is an open source asynchronous USB audio device class 2.0 implementation targeted to the Cortex---one option I've been toying with is porting audio-widget).
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