Drive NOS AD1865/62,PCM1704/02/63,TDA1541 from FIFO: Universal I2S-PCM driver board
Rather than I2S signals, most of R-2R NOS DACs (PCM63, AD1865, AD1862, PCM1704, PCM1702, TDA1541...) driven by LL/LR, DL, DR and BCK. I might be wrong, but to make it easier, I call them “PCM” signals.
Usually those signals are generated by digital filter chips (DF1704, PDM100, SM5842/43/47...). However, for applications such as NOS mode, software based up-sampling mode, or to interface directly with FIFO KIT, we don’t need that digital filter. In this case, how to design a low jitter I2S to PCM driver daughter board becomes an issue.
Zinsula, vzs and other members provided a lot of good suggestions on this driver board, I summarize those the requirements as blow
1. Support 16,18,20,24 bit PCM format
2. Support PCM63,AD1865,AD1862,PCM1704,PCM1702,TDA154 and other 2-2R DAC
3. L,R simultaneous timing, latching at same latching edge to eliminate L/R phase difference
4. Bit clock can be stopped after data shifted into DAC to reduce DAC noise floor further
5. Optional tail clocks after latching work for PCM17XX DAC
6. Optional one leading clock to “warm up” logic state machine(may not need in most of cases)
7. FPGA/CPLD based low jitter synchronized logic design clocked by MCLK only
8. High speed design capable for 384KHz Fs with maxima MCLK over 100MHz
9. Support dual mono DAC mode
10. Very high speed re-clocking at last stage optimized for low jitter performance
11. Daughter board architecture can stack on top of the FIFO clock board
I started this I2S to PCM driver daughter board project a couple of month ago. Now I’m almost done. Here are some previous progresses posted on the FIFO thread:
regal suggested me opening a new thread for this project. That makes sense. NOS DAC and DS DAC belong to different application. It’s not good mixing them up.
Will start evaluating this daughter board very soon.
This is a very interesting project. Can't wait until the PCB is available!
Testing result of AD1865 timing from a logical analyzer
To get the perfect timing, CLK will be stopped after 18 bit DL and DR shifted into AD1865. Left and right converting will be launched at the same moment of the falling edge of LLLR. All of the signals will keep low for rest of time to reduce the noise. Please refer to the first waveform from logic analyzer.
Rest jumpers: keep open
We can still go back to the traditional continue clock mode by just short another JCONT jumper. The second waveform is the result of this mode.
despite not being aimed at it, this could be interesting for use as an external filter for ESS in NOS mode
It is amazing how fast you can design and build boards.
AD1862 timing, Testing result from logic analyzer
AD1862 is a 20bit mono DAC. We need two AD1862, one for left, one for right.
To get the perfect timing, CLK will be stopped after 20 bit DATA shifted into AD1862. Left and right AD1862 converting will be launched at the same moment of the falling edge of LE. All of the signals will keep low for rest of time to reduce the noise. Please refer to the attached waveform from logic analyzer.
Rest jumpers: keep open
We can still go back to the traditional continue clock mode by just short another JCONT jumper.
The waveforms looks good!
I'm rejoicing the stoppable bit clock feature, with simple logic ICs would have been a pain to do it.
Seems that people started to read sampling theory docs and keep away from everything that contains the NOS word :rolleyes: (for good reason I must say)
They surely forget that free software like SoX can software oversample and do the "black magic" that only proprietary FPGA or DSP algorithms could do - like apodizing or minimum phase filters (google for who are using these...): e.g. Minimum Phase SoX settings
So the only thing needed is USB or SPDIF up to 192KHz and a NOS DAC :)
exactly, NOS dac, but not NOS signal path. computers have enough processing power to make light work of more demanding filters very difficult to achieve otherwise.
First of all, the 192k limit is small for oversampling of any kind. Even 384k that is the limit for Ian's board will not allow more than 8x os. But the thing is that we go again in all that mumbo-jumbo which is computer audio software.
The FPGA/DSP impementation of apodizing or minimum phase filters is not at all "black magic", it just pure math.
hmm what makes you think fpga is any less mumbo jumbo than a software implementation of the same thing? ians board will allow 384khz at 128x FS. for me I really dont care where it happens. but I think i'll let you guys have the promised land, or it'll turn into a turf war lol
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