Drive NOS AD1865/62,PCM1704/02/63,TDA1541 from FIFO: Universal I2S-PCM driver board

Yes, but without USB input, so you need the WaveIO.
USB connector is used to configure the device from PC (output type, output format, dithering and so on).

It can drive the TDA1541A in both I2S and simultaneous mode.
LRCK (and WS in I2S mode) is generated directly from the master clock, it does not cross the FPGA like in all similar devices, to keep it as clean as possible and free of jitter.
 
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the fifo stuff...
Iggy, when I listen to my AYA Dac connected to USB via Pedjas USB2PCM Board I don't miss the FIFO.

And, as I remember I preferred the music via
ALLO USB Bridge - AYA USB - AYA Dac over

Fully linear powered Pi3 - Fifopi - Ryan's i2s2pcm - AYA DAC.

Would have to do a critical listening session again, but I strongly think it was like that.

Cheers, Ernst
 
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Joined 2019
Thank you Ernst for the testimonial.


Raw my complete Iancanada didn't sounded too much good but when I understood it was very sensitive to the powersupply and also the powercap after the diodes rectifier bridges it get better : before the fifo : TS7A rectifier with main 3300 uF Elna purple basic cap as main smoothing diode then on the "clean-er" side of the Fifo : another TS7A reg but main is a FC cap 2200 uF. Then with the 1 uF acrylic cap on one of the two Crystek adaptator (removing all the X7R that sounded sterile despite it's certainly good with a scope) : it was sounding good. the I2StoPCM is powered with the same board that the Clock board !



My front-front-end is better than a Pi as it is the Lucian with Ndk crystal (a little like a JLSound) with the non isolator side but uf-l output. Then my front-front-front-fronnnnt end is a Synology DS210J which I surmise to be much cleaner that a Pi as the board has not the same limit due to the size and Synology maakes things good most of the time - and also the processor and ram are much lower than the Rpi.... Yes I still use its usb audio outputt....I'm a bit conservative as it was tunned for the"front-end PS + Aya Ps.)


Of course the Aya have the non 100 uF mode on the three TDA 1541A rails and only one smd cap on the smd of the -15V... While Pedja Rogic uses this trick now - my understanding- is it just use the 1200 uF cap of the manual tip but with 0.47 BG NX instead - so with not the FM cap in // ! I believe he did the same on the -/+5V while I'm not sure of that ! I do use different cap there on the 5Vs though... too much on a same cap is often not good -
 
Basically we are building the "SOTA system" (including amp and speakers) for our personal use, then, since we strongly believe in the architecture of each device as the right way to get the best performance, we are also trying to design some affordable projects to share with the audio community, based on the same architecture of the SOTA devices.

The FIFO Lite is an example, it share the same architecture of the SOTA FIFO but with some simplifications to get the cost affordable. The FIFO Lite is a 1 board device, while the SOTA FIFO will be a 2 chassis device with multiple board.

The rule of thumb: don't expect SOTA devices at Ian's prices, not on the market and neither in diy audio. At such that prices you get audio toys, surely enjoyable, but not the best one can design with the actual technology.
To explain better our thought take a look at the various oscillators available: the CCHD-957 is a toy that costs 25 Euro, the new Driscoll and Differential oscillators are SOTA devices, the best for digital audio ever, but they cost 10 time the Crystek as diy devices. Similar oscillators on the market are the MSB Femto Clock thet costs 19000 USD, or the Oscilloquartz and Wenzel oscillators (not for audio) that cost several USD thousands.

Don't never expect to get a SOTA oscillator for 25 Euro, you will get a toy at this price.

The same for a FIFO buffer, for a DAC and so on.
 
Hi Ian!

Is it possible to organize so-called "2wire" mode to use 2 channels (left+right) fpr doubling the sample rate? I have 1541A and I want to use it at x16 OS instead of x8 (it simply wont works at x16 as its BCK line is limited by 6.2MHz - it is OK, well known situation). I just thought... What I need is to use 2 pieces of TDA1541A, where two Iouts (left/right) of every stereo chip will works together (tighted to each other/paralleled connection) as a single channel. I do not very familiar with the internal logics of such approach, but it is similar (IMO) with conveyer principle, where one channel is shifted from other in time (at least) to make a single (but finally doubled in SR) signal. I do not sure but looks like dCS has implemented it in their devices and called it as dual-AES mode.
Similar approach was done in Kenwood DP-7090 and the summing from two, signal looks like:
Kenwood.jpg

So my question is. Is it possible to implement such approach (instead of balanced-mode) inside your I2S-PCM board (as there are un-used for me DRn/DLn outputs at least)? Will the internal DSP capabilitues be enough to make such a "trick"?

p.s. ecdesigns has implemented such too, but his approach was a bit incorrect in terms of the resulting wave:
ecdesigns.jpg
 
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Well, yes. My question was for Ian, is it possible to make such inside this i2s-pcm board or not? Interpolation is better. At finally it should be mixed from two (L/R) data-lines inside DAC chip into a single solid signal from DAC' both outputs. That means the doubled SR in fact (doubled amount of counts), over the "speed and settling time limitation" of DAC.
 
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If you mix left and right you get mono and you are back where you started with a single signal that is too fast at its higher sample rate. The point of dual AES or even SMUX adat is to slow things down. The single signal in linear interpolation made of multiple dacs is created in the analogue domain not the digital.
 
Of course I do not want to mix left and right channels to get mono. Task is to make a conveyer from DL and to feed the getted two specially prepared data lines on to both DR and DL inputs of the stereo DAC chip. And then to do the same operations with DR for another stereo DAC chip. It is instead of unnecesary (for me at least) balanced mode. I think Ian should understand what I mean and can give the answer by himself, is it possible or not within the capabilities of the used FPGA on this i2s-pcm converter.