Drive NOS AD1865/62,PCM1704/02/63,TDA1541 from FIFO: Universal I2S-PCM driver board - Page 19 - diyAudio
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Old 2nd January 2013, 11:35 AM   #181
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Quote:
Originally Posted by erin View Post
Please allow me to advise.
This board Ian is making will allow the option of a simultaneous output of offset binary Left and Right Data. For TDA1541 enthusiasts, and tinkerers, this will allow a person to create a dual mono TDA1541 board. Also possible is a dual differential, or balanced output TDA1541 board.

I know many people will be interested in these possibilities.

And it may be worth nothing, but I have read reports from those that have tried it, that the offset binary data input sounds better than the i2s.
I don't know, but I am keen to try it.

It will also allow the use of the TDA1540 chip.
In seeing pictures of PCM board, the connections (single TDA1541) would be as follows?:

LLLR to Pin 1 (LE/WS)
CLK to Pin 2 (BCK)
DL to Pin 3 (Data L)
DR to Pin 4 (Data R)
-5V to Pin 27

This would result in balanced output?...or did I misunderstand?
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Old 2nd January 2013, 11:46 AM   #182
erin is offline erin  Australia
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Originally Posted by qusp View Post
can a synchronous oversampled 4-8*FS output from this board be fed directly to the TDA for DEM reclocking, or is the only way to adjust the DEM by the use of specific capacitor values to adjust the normally free-running clock?
You need to divide the oversampled output by 2 or 4 respectively if you want to try DEM reclocking with oversampling.

Adjusting the capacitor value between pins 16 and 17 is another way to adjust the speed of the free running clock- but in which case it will not be synchronized. My 2c is that the Grundig method is the best sounding reclocking method. here I made some comments about the sound.
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Old 2nd January 2013, 11:51 AM   #183
erin is offline erin  Australia
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Quote:
Originally Posted by crobbins5421 View Post
In seeing pictures of PCM board, the connections (single TDA1541) would be as follows?:

LLLR to Pin 1 (LE/WS)
CLK to Pin 2 (BCK)
DL to Pin 3 (Data L)
DR to Pin 4 (Data R)
-5V to Pin 27

This would result in balanced output?...or did I misunderstand?
How you said will output stereo data.

For a single balanced channel you would have to for example, apply DL to (data L) and use an inverter to apply /DL to (data R) this will make a single chip with balanced output.
....And now you have me thinking if you need to invert the MSB on the inverted data as well. Does anyone else remember? The last time I inverted a binary number was at school and the part I needed to remember to answer this question leaked out my ear in my sleep...
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Last edited by erin; 2nd January 2013 at 12:00 PM.
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Old 2nd January 2013, 01:05 PM   #184
vzs is offline vzs  Europe
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Quote:
Originally Posted by erin View Post
...For a single balanced channel you would have to for example, apply DL to (data L) and use an inverter to apply /DL to (data R) this will make a single chip with balanced output...
For a single balanced channel you have to invert data and add one.

Ian, since the board has physical support for inverted data lines is it possible to squeeze balanced mode into the CPLD (add one to the inverted data lines)? As J2 header has some unused pins this feature could be optional.

Thanks, Zsolt

Last edited by vzs; 2nd January 2013 at 01:32 PM.
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Old 2nd January 2013, 01:17 PM   #185
qusp is offline qusp  Australia
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interesting, thanks for the replies guys, completely for curiosity, I dont plan to try it out but I do find the TDA internal architecture quite interesting all the same. i'm a complete no nothing when it comes to the 1541A. if I was to grab this board though it would mainly be for playing with a possible 1704 dac, OR toying with discrete ladders and even custom programmed FPGA based dac array clocking.
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Old 3rd January 2013, 01:27 AM   #186
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Quote:
Originally Posted by vzs View Post
For a single balanced channel you have to invert data and add one.

Ian, since the board has physical support for inverted data lines is it possible to squeeze balanced mode into the CPLD (add one to the inverted data lines)? As J2 header has some unused pins this feature could be optional.

Thanks, Zsolt
Hi Zsolt,

Yes it is possible. As you found, J2 reserved exactly for those purpose.

Regards,

Ian
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Old 3rd January 2013, 09:50 AM   #187
erin is offline erin  Australia
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Quote:
Originally Posted by vzs View Post
For a single balanced channel you have to invert data and add one.

Ian, since the board has physical support for inverted data lines is it possible to squeeze balanced mode into the CPLD (add one to the inverted data lines)? As J2 header has some unused pins this feature could be optional.

Thanks, Zsolt
Thanks, I knew there was a trick to it
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Last edited by erin; 3rd January 2013 at 09:53 AM.
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Old 3rd January 2013, 09:53 AM   #188
erin is offline erin  Australia
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Originally Posted by iancanada View Post
Hi Zsolt,

Yes it is possible. As you found, J2 reserved exactly for those purpose.

Regards,

Ian
Great!
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Old 3rd January 2013, 09:58 AM   #189
erin is offline erin  Australia
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Quote:
Originally Posted by vzs View Post
For a single balanced channel you have to invert data and add one.
Having looked again at offset binary, I think it would not matter if we don't add the one.
It would probably add more jitter trying to add the one........
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Last edited by erin; 3rd January 2013 at 10:05 AM.
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Old 3rd January 2013, 10:18 AM   #190
erin is offline erin  Australia
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Originally Posted by ryanj View Post
Qusp, the 1541 has limited bandwidth to about 6.5Mhz. The DEM has successfully been clocked from BCK at 2.8Mhz by several members following such designs as member "ecdesigns" (John Brown) has used in the past.
ecdesigns keeps changing his mind as to what sounds "better". He used to reclock his DEM really fast. Last I read he had gone to a slow, free running clock using a big capacitor between pins 16 and 17.
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