wm8804 jitter

[ku4ansito]

Does the jitter performance of WM8804 at 44.1k sample rate will be the same as at 48k/96k? (96k and 48k are multiple of 12MHz xtal) Any measurements of jitter at 44.1k?

[5th element]

The xtal, as far as I am aware, isn't really used in the actual clock reconstruction, it is used simply to operate the device. The internal PLL and then clock recovery circuitry, are what recreate the I2S signal/clock lines and they are adjusted around the S/PDIF rate.

Looked at another way, even though the 12MHz crystal might theoretically be a multiple of 48/96/192 in effect is isn't. The S/PDIF sampling frequency wont be exactly 48/96 or 192kHz, in much the same way the 12MHz crystal wont be exactly 12MHz either, this means that the two aren't really synchronous and the internal PLL and clock recovery system is required to adjust the internal rate of the S/PDIF receiver so that it matches that of the incoming signal.

Now as 12MHz is almost a direct multiple of 48/96/192, it could mean that the jitter levels for those sampling frequencies could be better then for 44.1kHz, but I don't know.

[ku4ansito]

Originally Posted by 5th element

Now as 12MHz is almost a direct multiple of 48/96/192, it could mean that the jitter levels for those sampling frequencies could be better then for 44.1kHz, but I don't know.

I think so and if jitter levels have any common with crystal frequency, it is better to use receiver in software mode with 11.2896 MHz crystal. Right?

[5th element]

Well if what we are assuming is correct then yeah, it would make sense to use it in software mode with a lower frequency crystal.

[s3tup]

Nope, WM uses the XTAL for generating a higher frequency clock by multiplication, which is then divided down to MCLK the WM outputs. It's DPLL, not a regular analog PLL.
The multiplication/division ratios are derived from FIFO fill level filtered by lowpass filter (in digital domain).

So, for better performance you'd like to throw a nice oscillator there.

DIR, CS and other receivers don't do that. That's why they are poor performers.

[chris719]

Has anyone been able to measure lower jitter when using an XO vs crystal?

[5th element]

Originally Posted by s3tup

Nope, WM uses the XTAL for generating a higher frequency clock by multiplication, which is then divided down to MCLK the WM outputs. It's DPLL, not a regular analog PLL.
The multiplication/division ratios are derived from FIFO fill level filtered by lowpass filter (in digital domain).

So, for better performance you'd like to throw a nice oscillator there.

DIR, CS and other receivers don't do that. That's why they are poor performers.

That is pretty much what I said. The PLL uses the XTAL as a reference from which it synthesizes the clocks that are then synchronous to the S/PDIF input.

If having a crystal of a multiple of the incoming sampling frequency will result in lower jitter then one that isn't I don't know.

[twest820]

Originally Posted by s3tup

CS and other receivers don't do that. That's why they are poor performers.

Actually, the CS8416 uses the same fractional PLL approach as the WM880x and is considerably better characterized---the OP will probably find it helpful to look at Cirrus AN-339 to understand how phase noise is shaped out of band and how phase detector updates affect overall jitter. As I've remarked on a couple other threads, Wolfson's period jitter spec is essentially irrelevant to WM880x baseband jitter. So what's needed to reason about the parts' relative performance is a characterization of WM880x comparable to what Cirrus has published in AN-339. However, if anyone's done measurements of the Wolfson's and published them I haven't been able to find them.

Haven't looked at the DIR parts much. If one really needs low jitter on a recovered clock probably the simplest solution is to use a jitter cleaner such as National's LMK04800 or TI's CDCE62002. DIYing a PCB which doesn't degrade those parts' performance is nontrivial, but that's a separate discussion. Something that would be interesting to do would be ABX testing between otherwise equivalent DACs, one with jitter cleaning and one without.

Originally Posted by 5th element

If having a crystal of a multiple of the incoming sampling frequency will result in lower jitter then one that isn't I don't know.

It depends on the PLL, particularly with the low PLL filter corner frequencies Wolfson uses---below the corner you get the underlying oscillator, above the corner you get the PLL. Integer PLLs generally have fewer spurs than fractional PLLs but that doesn't necessarily say anything about the spurs' distribution or height. Given Wolfson has elected not publish an equivalent to AN-339 I would tend to guess Wolfson's baseband jitter performance doesn't compare favorably with the CS8416. But, without measurements to confirm or deny, all one can do is enage in low confidence guesswork.

Originally Posted by chris719

Has anyone been able to measure lower jitter when using an XO vs crystal?

Broadly speaking, yes. However, I'm not aware of any baseband jitter measurements comparing XOs and crystals for SPDIF receive. It gets a little tricky; 44.1 clocks are most readily available from crystals while 48s are readily available in both. The difficulty with 48 series clocks is most recordings are 44.1 and the artifacts from sample rate conversion are generally quite a bit more significant than a couple picoseconds of jitter. So, for the mainline case of redbook audio playback most clocking choices are probably worse than a 256Fs 44.1 crystal. There are some exceptions---most notably synthesizing your own fixed point minimum phase interpolation filters and programming them into an ESS 901x DAC---but they come with their own limitations and restrictions.

[twest820]

Originally Posted by 5th element

Now as 12MHz is almost a direct multiple of 48/96/192, it could mean that the jitter levels for those sampling frequencies could be better then for 44.1kHz, but I don't know.

12MHz will require a fractional PLL. Jitter varies from part to part but recommended clocks tend to fall in the 20 to 25MHz range, which implies 512 Fs single speed clocks---22.5276MHz and 24.5760MHz for 44.1 and 48, respectively. 512 Fs 44.1 crystal and XO availablity is rather limited and tends to require throwing money at the parts. So mostly you end up looking at a 256 Fs---11.2896MHz---with perhaps a multiply by two via PLL to get 512 Fs depending on the clocking. For 48 there's good crystal and XO availablity 256 and 512 Fs.

The integer PLL conversion ratio between the clocks is the least common multiple of 44.1 and 48.0---441/480 = 147/160. Or the reciprocal if you need to generate a 48 series clock from a 44.1 crystal or XO. To use this directly a PLL core capable of a couple GHz is needed, but it's not uncommon for PLLs to top out around 500MHz. That means you end up predividing, resulting in a reduced PDF (phase detector frequency / phase detector update rate) and, typically, more jitter. But it varies from part to part---manufacturers tend to recommend using the highest feasible PDF but National, notably, does not. The tradeoff therefore often looks like 147/160 with a reduced PDF versus a fractional PLL with a higher PDF. Which has lower phase noise? It depends on the PLL, the ratios used, and even component to component variations. The reliable way to figure out the optimum is to program up the clock generator different ways with (potentially) different crystals and XOs and measure the phase noise.

[s3tup]

For wolfson -
http://www.diyaudio.org.ua/download/file.php?id=781 - doc from AES

Related patent:
http://www.google.com.ua/patents/dow...erview_r&cad=0



CS'8416 clearly shows the PLL uses analog, externally passively filtered VCO. The control of VCO IS analog. The same is true for the AN-339.
So citrus is far away of being wolfson.

Wolfson does so in digital domain in better way.