The xtal, as far as I am aware, isn't really used in the actual clock reconstruction, it is used simply to operate the device. The internal PLL and then clock recovery circuitry, are what recreate the I2S signal/clock lines and they are adjusted around the S/PDIF rate.
Looked at another way, even though the 12MHz crystal might theoretically be a multiple of 48/96/192 in effect is isn't. The S/PDIF sampling frequency wont be exactly 48/96 or 192kHz, in much the same way the 12MHz crystal wont be exactly 12MHz either, this means that the two aren't really synchronous and the internal PLL and clock recovery system is required to adjust the internal rate of the S/PDIF receiver so that it matches that of the incoming signal.
Now as 12MHz is almost a direct multiple of 48/96/192, it could mean that the jitter levels for those sampling frequencies could be better then for 44.1kHz, but I don't know.
Looked at another way, even though the 12MHz crystal might theoretically be a multiple of 48/96/192 in effect is isn't. The S/PDIF sampling frequency wont be exactly 48/96 or 192kHz, in much the same way the 12MHz crystal wont be exactly 12MHz either, this means that the two aren't really synchronous and the internal PLL and clock recovery system is required to adjust the internal rate of the S/PDIF receiver so that it matches that of the incoming signal.
Now as 12MHz is almost a direct multiple of 48/96/192, it could mean that the jitter levels for those sampling frequencies could be better then for 44.1kHz, but I don't know.
I think so and if jitter levels have any common with crystal frequency, it is better to use receiver in software mode with 11.2896 MHz crystal. Right?
Nope, WM uses the XTAL for generating a higher frequency clock by multiplication, which is then divided down to MCLK the WM outputs. It's DPLL, not a regular analog PLL.
The multiplication/division ratios are derived from FIFO fill level filtered by lowpass filter (in digital domain).
So, for better performance you'd like to throw a nice oscillator there.
DIR, CS and other receivers don't do that. That's why they are poor performers.
The multiplication/division ratios are derived from FIFO fill level filtered by lowpass filter (in digital domain).
So, for better performance you'd like to throw a nice oscillator there.
DIR, CS and other receivers don't do that. That's why they are poor performers.
That is pretty much what I said. The PLL uses the XTAL as a reference from which it synthesizes the clocks that are then synchronous to the S/PDIF input.
If having a crystal of a multiple of the incoming sampling frequency will result in lower jitter then one that isn't I don't know.
Actually, the CS8416 uses the same fractional PLL approach as the WM880x and is considerably better characterized---the OP will probably find it helpful to look at Cirrus AN-339 to understand how phase noise is shaped out of band and how phase detector updates affect overall jitter. As I've remarked on a couple other threads, Wolfson's period jitter spec is essentially irrelevant to WM880x baseband jitter. So what's needed to reason about the parts' relative performance is a characterization of WM880x comparable to what Cirrus has published in AN-339. However, if anyone's done measurements of the Wolfson's and published them I haven't been able to find them.
Haven't looked at the DIR parts much. If one really needs low jitter on a recovered clock probably the simplest solution is to use a jitter cleaner such as National's LMK04800 or TI's CDCE62002. DIYing a PCB which doesn't degrade those parts' performance is nontrivial, but that's a separate discussion. Something that would be interesting to do would be ABX testing between otherwise equivalent DACs, one with jitter cleaning and one without.
It depends on the PLL, particularly with the low PLL filter corner frequencies Wolfson uses---below the corner you get the underlying oscillator, above the corner you get the PLL. Integer PLLs generally have fewer spurs than fractional PLLs but that doesn't necessarily say anything about the spurs' distribution or height. Given Wolfson has elected not publish an equivalent to AN-339 I would tend to guess Wolfson's baseband jitter performance doesn't compare favorably with the CS8416. But, without measurements to confirm or deny, all one can do is enage in low confidence guesswork.
Broadly speaking, yes. However, I'm not aware of any baseband jitter measurements comparing XOs and crystals for SPDIF receive. It gets a little tricky; 44.1 clocks are most readily available from crystals while 48s are readily available in both. The difficulty with 48 series clocks is most recordings are 44.1 and the artifacts from sample rate conversion are generally quite a bit more significant than a couple picoseconds of jitter. So, for the mainline case of redbook audio playback most clocking choices are probably worse than a 256Fs 44.1 crystal. There are some exceptions---most notably synthesizing your own fixed point minimum phase interpolation filters and programming them into an ESS 901x DAC---but they come with their own limitations and restrictions.
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12MHz will require a fractional PLL. Jitter varies from part to part but recommended clocks tend to fall in the 20 to 25MHz range, which implies 512 Fs single speed clocks---22.5276MHz and 24.5760MHz for 44.1 and 48, respectively. 512 Fs 44.1 crystal and XO availablity is rather limited and tends to require throwing money at the parts. So mostly you end up looking at a 256 Fs---11.2896MHz---with perhaps a multiply by two via PLL to get 512 Fs depending on the clocking. For 48 there's good crystal and XO availablity 256 and 512 Fs.
The integer PLL conversion ratio between the clocks is the least common multiple of 44.1 and 48.0---441/480 = 147/160. Or the reciprocal if you need to generate a 48 series clock from a 44.1 crystal or XO. To use this directly a PLL core capable of a couple GHz is needed, but it's not uncommon for PLLs to top out around 500MHz. That means you end up predividing, resulting in a reduced PDF (phase detector frequency / phase detector update rate) and, typically, more jitter. But it varies from part to part---manufacturers tend to recommend using the highest feasible PDF but National, notably, does not. The tradeoff therefore often looks like 147/160 with a reduced PDF versus a fractional PLL with a higher PDF. Which has lower phase noise? It depends on the PLL, the ratios used, and even component to component variations. The reliable way to figure out the optimum is to program up the clock generator different ways with (potentially) different crystals and XOs and measure the phase noise.
For wolfson -
http://www.diyaudio.org.ua/download/file.php?id=781 - doc from AES
Related patent:
http://www.google.com.ua/patents/do...QPlRQqkSY4t1j9G2Q&source=gbs_overview_r&cad=0
CS'8416 clearly shows the PLL uses analog, externally passively filtered VCO. The control of VCO IS analog. The same is true for the AN-339.
So citrus is far away of being wolfson.
Wolfson does so in digital domain in better way.
http://www.diyaudio.org.ua/download/file.php?id=781 - doc from AES
Related patent:
http://www.google.com.ua/patents/do...QPlRQqkSY4t1j9G2Q&source=gbs_overview_r&cad=0
CS'8416 clearly shows the PLL uses analog, externally passively filtered VCO. The control of VCO IS analog. The same is true for the AN-339.
So citrus is far away of being wolfson.
Wolfson does so in digital domain in better way.
Agree the control loops differ but that doesn't really say anything about WM880x baseband jitter; assuming the parts follow Wolfson's patent (which seems reasonable) their output clock is taken from an analog PLL. Without phase noise measurements there's not really any good way to reason about PLL quality or spur audibility---a hybrid PLL isn't necessarily lower jitter than an analog PLL (if it were Wolfson's period jitter spec would be femtoseconds rather than picoseconds).
Jean-Paul, do you have measurements or ABX/double blind results?
Someone somewhere over Russia did the DIR9001 Vs WM8804/5 battle in proper implementations (the guy designs DACs a lot) - the conclusion was "DIR9001 and WMs are the same with a low-jitter good source. WMs are better when poor source is involved.".
WMs do have a transmitter too, for free. A great building block to make the system synchronous, and therefore virtually jitter-less.
DIRs do have 5v outputs, and do have 384Fs MCLK, rendering 'em suitable for vintage DACs and digital filters.
By the way, there is a measured comparison between regular receiver technology and WM's (the "regular receiver technology" has no name, but i guess it's the CS
).
WMs do have a transmitter too, for free. A great building block to make the system synchronous, and therefore virtually jitter-less.
DIRs do have 5v outputs, and do have 384Fs MCLK, rendering 'em suitable for vintage DACs and digital filters.
By the way, there is a measured comparison between regular receiver technology and WM's (the "regular receiver technology" has no name, but i guess it's the CS
).
'coz it's in russian and is somewhere deep in the vegalab.ru
Google translator may help you
ñ ïîÿâëåíèåì òàêîãî çàìå÷àòåëüíîãî ÑÏÄÈô ïðèåìíèêà, êàê WM8804
Per measurements: integrated jitter in 30Hz-15kHz range, on the bench (ideal conditions, really far from real world):
- DIR9001, 3 sample ICs, circa 65ps
- WM8804, 6 sample ICs, circa 62ps
Google translator may help you
ñ ïîÿâëåíèåì òàêîãî çàìå÷àòåëüíîãî ÑÏÄÈô ïðèåìíèêà, êàê WM8804
Per measurements: integrated jitter in 30Hz-15kHz range, on the bench (ideal conditions, really far from real world):
- DIR9001, 3 sample ICs, circa 65ps
- WM8804, 6 sample ICs, circa 62ps
Wow what fun with Google Translate ! So the guys there state that :
- WM8804/5 and DIR9001 are both better than CS8416
- DIR9001 and WM8804/5 practically give the same results with low jitter sources
- WM8804/5 work better with less optimal sources when compared with DIR9001
- WM8804/5 often work OK contrary to DIR9001 (regarding sensitivity of the input circuit)
Some things are experienced the same in various parts of the globe.
- WM8804/5 and DIR9001 are both better than CS8416
- DIR9001 and WM8804/5 practically give the same results with low jitter sources
- WM8804/5 work better with less optimal sources when compared with DIR9001
- WM8804/5 often work OK contrary to DIR9001 (regarding sensitivity of the input circuit)
Some things are experienced the same in various parts of the globe.
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Thanks, s3tup (for those not interested in the whole thread over at vegalab, see post 17). Cirrus uses a 40kHz bandwidth for measuring baseband jitter so the 123ps given in AN-339 is pretty much in the same space as the DIR9001 and WM8804 measurements with respect to intrinsic baseband jitter. Without knowing the shape of the phase noise and the jitter of the measurement gear used there's really no way to say which would be best on a clean source. For a jittery source I would tend to expect the Wolfson parts to tend come out ahead as they have the lowest PLL bandwidth---100Hz versus about 10kHz for the DIR9001 and CS8416. For a clean source it's actually possible the DIR9001 and CS8416 would be lower jitter than the WM880x since they'll lock to the source over a wider bandwidth.
I've had a chance to read through Wolfson's patent and AES paper. Looks like the way the WM880x is implemented is the PLL locks to crystal and the control loop steers the PLL's fractional divider with a 1Hz bandwidth (rather lower than the 100Hz I've seen mentioned elsewhere for the parts) to match the clocks. As usual, the divide introduces one PLL clock's worth of jitter---nominally 10ns as the recommended frequency in the PLL core is F2 = 90 to 100MHz. If I've got my maths right the resulting spurs will fall in the low tens of MHz for typical configurations of the part. Wolfson makes no mention of attenuating these via the analog lowpass in the control loop but I would imagine they do so as this is fairly standard practice.
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