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Old 17th July 2012, 05:43 AM   #11
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Things can be simple without much words or discussion. Just try them both with the same DAC chip and compare. You will forget about using CS8416 very fast.
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Old 17th July 2012, 05:21 PM   #12
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Originally Posted by s3tup View Post
Wolfson does so in digital domain in better way.
Agree the control loops differ but that doesn't really say anything about WM880x baseband jitter; assuming the parts follow Wolfson's patent (which seems reasonable) their output clock is taken from an analog PLL. Without phase noise measurements there's not really any good way to reason about PLL quality or spur audibility---a hybrid PLL isn't necessarily lower jitter than an analog PLL (if it were Wolfson's period jitter spec would be femtoseconds rather than picoseconds).

Jean-Paul, do you have measurements or ABX/double blind results?
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Old 17th July 2012, 05:35 PM   #13
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I don't know about WM8804 but people have measured CS8416 and if I recall correctly they were poor in terms of jitter, beaten by CS8414 and CS8412 even.
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Old 17th July 2012, 06:55 PM   #14
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Well CS's application note shows the CS8414 beating the CS8416 unless the CS8416 is configured correctly. Now of course one would expect the comparisons to be between 16s configured in the right way, but I wouldn't count on it.
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Old 17th July 2012, 07:08 PM   #15
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Someone somewhere over Russia did the DIR9001 Vs WM8804/5 battle in proper implementations (the guy designs DACs a lot) - the conclusion was "DIR9001 and WMs are the same with a low-jitter good source. WMs are better when poor source is involved.".

WMs do have a transmitter too, for free. A great building block to make the system synchronous, and therefore virtually jitter-less.
DIRs do have 5v outputs, and do have 384Fs MCLK, rendering 'em suitable for vintage DACs and digital filters.

By the way, there is a measured comparison between regular receiver technology and WM's (the "regular receiver technology" has no name, but i guess it's the CS ).
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Old 17th July 2012, 08:06 PM   #16
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Originally Posted by s3tup View Post
Someone somewhere over Russia did the DIR9001 Vs WM8804/5 battle in proper implementations (the guy designs DACs a lot) - the conclusion was "DIR9001 and WMs are the same with a low-jitter good source. WMs are better when poor source is involved.".
Got a link? Not having any luck searching on the quote.
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Old 17th July 2012, 08:21 PM   #17
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'coz it's in russian and is somewhere deep in the vegalab.ru

Google translator may help you
с появлением такого замечательного СПДИф приемника, как WM8804

Per measurements: integrated jitter in 30Hz-15kHz range, on the bench (ideal conditions, really far from real world):
- DIR9001, 3 sample ICs, circa 65ps
- WM8804, 6 sample ICs, circa 62ps
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Old 17th July 2012, 08:49 PM   #18
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Wow what fun with Google Translate ! So the guys there state that :

- WM8804/5 and DIR9001 are both better than CS8416
- DIR9001 and WM8804/5 practically give the same results with low jitter sources
- WM8804/5 work better with less optimal sources when compared with DIR9001
- WM8804/5 often work OK contrary to DIR9001 (regarding sensitivity of the input circuit)

Some things are experienced the same in various parts of the globe.
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Last edited by jean-paul; 17th July 2012 at 08:58 PM.
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Old 18th July 2012, 02:04 AM   #19
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Thanks, s3tup (for those not interested in the whole thread over at vegalab, see post 17). Cirrus uses a 40kHz bandwidth for measuring baseband jitter so the 123ps given in AN-339 is pretty much in the same space as the DIR9001 and WM8804 measurements with respect to intrinsic baseband jitter. Without knowing the shape of the phase noise and the jitter of the measurement gear used there's really no way to say which would be best on a clean source. For a jittery source I would tend to expect the Wolfson parts to tend come out ahead as they have the lowest PLL bandwidth---100Hz versus about 10kHz for the DIR9001 and CS8416. For a clean source it's actually possible the DIR9001 and CS8416 would be lower jitter than the WM880x since they'll lock to the source over a wider bandwidth.
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Old 9th August 2012, 02:36 AM   #20
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I've had a chance to read through Wolfson's patent and AES paper. Looks like the way the WM880x is implemented is the PLL locks to crystal and the control loop steers the PLL's fractional divider with a 1Hz bandwidth (rather lower than the 100Hz I've seen mentioned elsewhere for the parts) to match the clocks. As usual, the divide introduces one PLL clock's worth of jitter---nominally 10ns as the recommended frequency in the PLL core is F2 = 90 to 100MHz. If I've got my maths right the resulting spurs will fall in the low tens of MHz for typical configurations of the part. Wolfson makes no mention of attenuating these via the analog lowpass in the control loop but I would imagine they do so as this is fairly standard practice.
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