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Old 19th July 2012, 09:49 PM   #111
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Quote:
Originally Posted by chaparK View Post
...
Provided these conditions above, yes you can use Symphony Studio and write your own code.
Is that true also for Sigma Studio (in case your board is based on Analog Devices)?

Cheers!
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Old 19th July 2012, 09:53 PM   #112
chaparK is offline chaparK  Luxembourg
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Originally Posted by dudaindc View Post
Is that true also for Sigma Studio (in case your board is based on Analog Devices)?

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Hmm... That board is based on Freescale's dual-core 500 MIPS DSP56725, not any of Analogue Devices' chips.
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Old 19th July 2012, 09:55 PM   #113
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Hmm... That board is based on Freescale's dual-core 500 MIPS DSP56725, not any of Analogue Devices' chips.
I should have that one (and only) brain cell engaged before typing...

Even more interested now...
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Old 19th July 2012, 09:56 PM   #114
chaparK is offline chaparK  Luxembourg
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I should have that one (and only) brain cell engaged before typing...
No worries
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Old 20th July 2012, 03:42 AM   #115
qusp is offline qusp  Australia
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Originally Posted by chaparK View Post
There's one central clock, and from this clock is derived the internal DSP working sampling frequency, which can be 48, 96 or 192 kHz.
hmm.. as I thought

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1. If you don't want to resample the input stream, then you must resample the processing - so that in the end you're only shifting the resampling elsewhere.
Imagine you specify a delay which is 41 sampling periods at 44.1 kHz, but the input stream is 48kHz. That's 44.625 clock periods at 48 kHz, we agree right? Shall the DSP 'resample' that delay to 44 or to 45 sampling clocks?
Imagine now the case of a FIR filter designed by yourself and consisting in 342 coefficients at 44.1 kHz. But the input stream happens to be 96 kHz. Well then the DSP requires 744.489 coefficients derived from the original 342 through ... resampling of the original FIR.
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What I mean is that there's going to be resampling anyway if one wants to support various sampling frequencies.
so its not possible to have N different FIRs? i'm not overly savvy (understatement) in that area. I guess I just assumed the FIR would be based on the samplerate, not the other way around. actually more accurately, I presumed the filter itself and that process did not have any reference at all to the output clock, being resolution independent and acting on a sample by sample basis in processor memory; only when it came to spitting it out did the result spat out onto each clock tick. thats not based on any knowledge just how I figured it would work

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2. If we want to support natively N standard audio rates (say N = 7 for 32, 44.1, 48, 88.2, 96, 176.4 and 196 kHz) then the DSP must store N coefficient sets for each of the supported sampling frequency. These coefficients are resampled versions of an original model as with seen in point 1.
yeah but thats not insurmountable is it, given the below points are well taken care of?

Quote:
3. The next problem is that we must detect the input rate in order to decide what coefficient set to apply. With SPDIF that's alright, we could use the PLL lock status and wait until the clock settles, then extract the sampling frequency. But how would we do that for I2S inputs?
not a problem, both of my i2s sources have 2 clocks (one has 3, one 12mHz TCXO for USB) there is a header from which the chosen speed for MCK can be pulled. it will set logic high or low depending. its a mechanism used for both selecting the clock, as well as displaying the samplerate on a display

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And now, what if there's a bug in the system: the input is 44.1 kHz but the system has detected 196 kHz and picked the wrong coefficient set, the net result being that we blew your new ribbon tweeters ...
yeah well if that happened with my source too it would suck, but it doesnt

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In short, you shouldn't worry about resampling the audio: the THD+N of resamplers is much lower than what your DAC can do, and resampling is here around anyway if you wish to support various sampling rates.
maybe I shouldnt, but I do

Last edited by qusp; 20th July 2012 at 04:03 AM.
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Old 21st July 2012, 01:24 PM   #116
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This is an interesting project!
Can you already tell some details about specifications like Dynamic Range, CMMR, Crosstalk and Distortion?
How do you like to design the volume control? Separate ICīs like PGA behind the DSP?
Regards
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Old 21st July 2012, 04:46 PM   #117
chaparK is offline chaparK  Luxembourg
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Originally Posted by qusp View Post
hmm.. as I thought

[...]

maybe I shouldnt, but I do
Ok mate we'll find a way to please you on that issue by allowing to use an external clock It's not easy to keep you satisfied you know I'll made the hardware change to make this possible but software management will come later with a second release. Note that with this change it's your responsibility to supply a clean clock (I2S).

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Originally Posted by mEon View Post
This is an interesting project!
Can you already tell some details about specifications like Dynamic Range, CMMR, Crosstalk and Distortion?
How do you like to design the volume control? Separate ICīs like PGA behind the DSP?
Regards
Thanks for your interest!
I don't have any measurement at that point. I need to meet a long time buddy, ask him to forgive me for not contacting him for so long and maybe ask him if he still has his AudioP
Analogue volume control is taken care of with CS3318 (or CS3308), obviously separate from DSP.
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Old 21st July 2012, 07:03 PM   #118
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Do you have a list of software functions ?
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Old 22nd July 2012, 03:41 AM   #119
qusp is offline qusp  Australia
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Originally Posted by chaparK View Post
Ok mate we'll find a way to please you on that issue by allowing to use an external clock It's not easy to keep you satisfied you know I'll made the hardware change to make this possible but software management will come later with a second release. Note that with this change it's your responsibility to supply a clean clock (I2S).
thanks!, thats cool, I wont be till the second release anyway I wouldnt think, as i'm on mac OS Lion, i'll use linux or win in emulation if I have to, but I would really prefer not to. depends on how that impacts the timing. All in all i'm in no rush

No, not easy to please I know, I like to upgrade to systems that are better than or comparable + more convenient than what I already have =) I think you'll find there will be more than me who will appreciate the ability to maintain synchronous dual masterclock and I would expect more sales because of it.

clean clocks? not a problem, i'm using a clock + clock buffer that totals less than a pS

Last edited by qusp; 22nd July 2012 at 03:54 AM.
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Old 22nd July 2012, 09:16 AM   #120
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Hello chaparK

Here in germany we are also interested in your project.
I will make some advertisement in the DIY-Community.

Greetings from Germany
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