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Old 17th July 2012, 02:49 PM   #101
enantra is offline enantra  Spain
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hi chapark,
i am interested!
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Old 17th July 2012, 05:06 PM   #102
chaparK is offline chaparK  Luxembourg
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Originally Posted by dudaindc View Post
I am joining others here and I am definitely interested...

Cheers!
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Originally Posted by enantra View Post
hi chapark,
i am interested!
Thanks for your expression of interest.
More information to follow.
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Old 17th July 2012, 05:41 PM   #103
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Will there be some sort of preorder to make sure that you can sell all
that you manufacture ?
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Old 17th July 2012, 06:54 PM   #104
chaparK is offline chaparK  Luxembourg
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Originally Posted by dahlberg View Post
Will there be some sort of preorder to make sure that you can sell all
that you manufacture ?
No I don't think so.

I'll just start offering the product when it's working to specs and when the boards are available. I'll keep you informed but target date is 1st October for the Windows release. Maybe earlier
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Old 17th July 2012, 07:54 PM   #105
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Ok.
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Old 18th July 2012, 06:39 PM   #106
qusp is offline qusp  Australia
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have to admit I didnt think of this before, but it would seem that bitperfect transfer to the DSP is not possible with your board, it didnt sink in before, but you only have one clock, I suppose this can be solved by using external clock, but how is the data clocked out of the DSP, will having 2 audio clocks for the 2 integers 22.1x and 24x for the dacs be enough, or will the data have already been resampled to suit 24x for everything? obviously the DSP resamples to a higher bitrate and bitdepth for processing, but can it still be based on 22.1x?

this is IMO one of the big failings of the miniDSP and it would be nice to avoid if possible. sorry if i've missed something
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Old 19th July 2012, 01:49 AM   #107
chaparK is offline chaparK  Luxembourg
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Originally Posted by qusp View Post
have to admit I didnt think of this before, but it would seem that bitperfect transfer to the DSP is not possible with your board, it didnt sink in before, but you only have one clock, I suppose this can be solved by using external clock, but how is the data clocked out of the DSP, will having 2 audio clocks for the 2 integers 22.1x and 24x for the dacs be enough, or will the data have already been resampled to suit 24x for everything? obviously the DSP resamples to a higher bitrate and bitdepth for processing, but can it still be based on 22.1x?

this is IMO one of the big failings of the miniDSP and it would be nice to avoid if possible. sorry if i've missed something
There's one central clock, and from this clock is derived the internal DSP working sampling frequency, which can be 48, 96 or 192 kHz.

What's coming in from the digital domain goes through a sample rate converter in order to adapt the input rate to the DSP rate. There's no worry to have about that because sample rate converters exhibit extremely low THD+N - well below the level of your ouptut DAC's THD+N, whatever DAC it is.

Now, let's imagine that we follow you and decide to use the clock derived from the input stream. Then there are 3 major problems:

1. If you don't want to resample the input stream, then you must resample the processing - so that in the end you're only shifting the resampling elsewhere.
Imagine you specify a delay which is 41 sampling periods at 44.1 kHz, but the input stream is 48kHz. That's 44.625 clock periods at 48 kHz, we agree right? Shall the DSP 'resample' that delay to 44 or to 45 sampling clocks?
Imagine now the case of a FIR filter designed by yourself and consisting in 342 coefficients at 44.1 kHz. But the input stream happens to be 96 kHz. Well then the DSP requires 744.489 coefficients derived from the original 342 through ... resampling of the original FIR.

What I mean is that there's going to be resampling anyway if one wants to support various sampling frequencies.

2. If we want to support natively N standard audio rates (say N = 7 for 32, 44.1, 48, 88.2, 96, 176.4 and 196 kHz) then the DSP must store N coefficient sets for each of the supported sampling frequency. These coefficients are resampled versions of an original model as with seen in point 1.

3. The next problem is that we must detect the input rate in order to decide what coefficient set to apply. With SPDIF that's alright, we could use the PLL lock status and wait until the clock settles, then extract the sampling frequency. But how would we do that for I2S inputs?
And now, what if there's a bug in the system: the input is 44.1 kHz but the system has detected 196 kHz and picked the wrong coefficient set, the net result being that we blew your new ribbon tweeters ...

In short, you shouldn't worry about resampling the audio: the THD+N of resamplers is much lower than what your DAC can do, and resampling is here around anyway if you wish to support various sampling rates.

Last edited by chaparK; 19th July 2012 at 02:00 AM.
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Old 19th July 2012, 08:36 PM   #108
_Wim_ is offline _Wim_  Belgium
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Can the board also be programmed with Symphony Studio for those who want to learn some DSP programming?

This would be much better then buying some generic evaluation board... And hopefully a bit cheaper also :-)
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Old 19th July 2012, 08:56 PM   #109
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Interested!
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Old 19th July 2012, 09:44 PM   #110
chaparK is offline chaparK  Luxembourg
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Can the board also be programmed with Symphony Studio for those who want to learn some DSP programming?

This would be much better then buying some generic evaluation board... And hopefully a bit cheaper also :-)
There's a JTAG header on board. It's your responsibility to provide the hardware between the DSP board and your computer.
The peripherals (ADC/DAC, SPDIF outs etc) are configured by the micro-controller. So you will need to handle that portion of code as well, as I suppose you would want to hear your processing.

Provided these conditions above, yes you can use Symphony Studio and write your own code.

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Interested!
Cool!
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