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Old 1st June 2012, 11:34 AM   #1
Ciorny is offline Ciorny  Austria
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Default Digital buffer inverted or non-inverted

Im starting a new project DAC with the following main components:

SRC4392 (DIR + sample rate converter)
2x WM8741/channel (dual mono)
ADA4627 op-amps (RCA out)

Now I am considering whether I should use inverted (like 74VHC04) or non inverted (like 74VHC04) digital-buffers between SRC4392 & 4x WM8741.
Any ideas or impact on Jitter?

Thanks

Last edited by Ciorny; 1st June 2012 at 02:48 PM.
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Old 2nd June 2012, 02:06 AM   #2
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Please post a schematic. It's unclear where buffers would be needed.

Assuming the input's to the DIR I would route the 4392's port A to one 8741 and port B to the other. I would not enable the ASRC as it's a fast rolloff type and my ABX testing found the extended impulse response of such filters creates more subjective degradation than changing the sample rate avoids. Used in this configuration the SRC4392's basically an expensive CS8416 or WM8805 with more jitter on the recovered clock. So if this happens to be your scenario you might consider those parts.

Any particular reason for ADA4627s as opposed to lower cost, higher performance parts such as the LME49710 (or LME49980 if you really need JFETs)?
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Old 2nd June 2012, 11:24 AM   #3
Ciorny is offline Ciorny  Austria
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The whole DAC project is only just a consideration now; I have not drawn a schematic yet, but Ill do next.

The buffers should be placed similar to Arcam´s schematics (see attachments: Arcam_CD_192 drawn on the left, Arcam_CD_37 drawn in the middle), but settled between SRC4392 and WM8741: I think it should be beneficial if using more than one DAC chip.
I personally tend more to the inverting buffers: 2 x inverting buffers in serial for each channel should work.

The SRC4392 I have chosen on the basis of the possibility of input signals up to 192khz, the routing of port A & B (dual mono) with integrated ASRC.

Now according your statements I become unsafe about this chip:
If the jitter is real that bad, should I choose better other components like CS8416 + SRC4192 + WM8741?

A year ago, I completed a heavy modified Gigawork (CS8416, CS8421, CS4398) and Im still happy with that: anyway I'm look forward for something better.

Regarding ADA4627:
I tried several op-amps in my old DAC (OPA627BP, LME49710, AD797B,....), but the ADA4627 gives me subjectively the best sound quality so far.
.
Attached Files
File Type: pdf arcam_cd37_diva_sm.pdf (99.6 KB, 66 views)
File Type: pdf arcam_cd192_sch.pdf (85.1 KB, 49 views)
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Old 2nd June 2012, 12:36 PM   #4
wwenze is offline wwenze  Singapore
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I wonder about that too, biphase-marked-code shouldn't mind if it is inverted.
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Old 3rd June 2012, 06:54 PM   #5
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Quote:
Originally Posted by Ciorny View Post
If the jitter is really that bad, should I choose better components like CS8416 + SRC4192 + WM8741?
The best way to answer that is to do an end to end analysis of the intended playback system to work out the DAC THD and DNR required to hit your design goals. From there you can derive an approximate jitter budget. Some fudgy math will be involved in estimating the amount of jitter rejection provided by the DAC's noise shaping but it'll probably rule in or out enough parts to provide convergence to a particular design space.

From a general design standpoint if the playback system requires the 3dB DNR increase from mono operation on an 8741 it's likely easier to fix the problem elsewhere. -122dBV RMS is about the audio band Johnson noise of a 2k resistor, with all of the sub-microvolt noise management fiddliness that implies. Similarly, a -128dB jitter floor at 192kHz requires 4ps or less total jitter, though you can probably count on the DAC to provide around 15dB jitter rejection, suggesting an XO like a Fox Xpresso is probably just good enough in the typical case (your call on how much margin to allow for process corners). If you need less than a couple hundred ps total jitter in a recovered clock look at jitter cleaners such as the CDCE62002 or LMK04800.

The buffers you mention on the Arcams are I2S/DSD fanout, not MCLK, and therefore non-critical. The digital input lines do need to be quiet enough to avoid coupling from them blowing the DAC noise floor but my bet would be the dominant signal quality factor is how much time you spend optimizing the source termination resistors---most likely the added jitter from reflections a bus routed net is lower than the jitter from buffering. One would need to route the board and do extracted sims to verify.

Last edited by twest820; 3rd June 2012 at 07:06 PM.
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