Build Thread for TPA BIII + Ian Async I2S FIFO + OPC NTD1 + Salas SSLV - Page 40 - diyAudio
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Old 3rd January 2013, 05:43 AM   #391
qusp is offline qusp  Australia
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no it wont work without the clock board, where would it get its clock....

it still needs to take a clock from the single clock board for operation, you can take the i2s directly from the fifo board, which simply means you get an output with the jitter of the clock + the jitter of the FPGA, taking the output from the clock board means its taking the output from the fifo board and reclocking it, meaning the jitter is that of the clock itself, plus the jitter of the flipflop/clock buffer

Last edited by qusp; 3rd January 2013 at 05:46 AM.
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Old 3rd January 2013, 06:03 AM   #392
karvid is offline karvid  Sweden
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Quote:
Originally Posted by qusp View Post
no it wont work without the clock board, where would it get its clock....

it still needs to take a clock from the single clock board for operation, you can take the i2s directly from the fifo board, which simply means you get an output with the jitter of the clock + the jitter of the FPGA, taking the output from the clock board means its taking the output from the fifo board and reclocking it, meaning the jitter is that of the clock itself, plus the jitter of the flipflop/clock buffer
Sorry I wasn't so clear.
Yes, I mean with one of the clock board connected, but the I2S signal taken directly from the Fifo board. But as you say I don't get any advantages with this. So I have to wait for a working dual clock then.
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Old 3rd January 2013, 07:57 AM   #393
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I know this sounds too simplisitic but I had a similar problem before I realized that the clocks were not well inserted into their sockets.If I recall, I think they were even inverted.

You can also check that the voltages are correct on the clock board.
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Old 3rd January 2013, 07:59 AM   #394
qusp is offline qusp  Australia
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yeah I get the feeling this is going to be one of those Fonzie moments
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Old 3rd January 2013, 08:03 AM   #395
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Another simiar problem I had was that my salas shunt was not givng enough current for the fifo and clock board. It was also powering the subu dac. Gave more current and all was fine.
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Old 3rd January 2013, 08:56 AM   #396
qusp is offline qusp  Australia
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5v is a bit low too
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Old 3rd January 2013, 02:04 PM   #397
karvid is offline karvid  Sweden
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I just checked the clock and the legs are well inserted and in correct orientation.

I tried to rais the voltage to 6 VDC and it didn't make any different. The voltage to both clocks is 3,286 VDC in both cases (5VDC or 6VDC in) and the same for both clocks.
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Old 3rd January 2013, 02:11 PM   #398
karvid is offline karvid  Sweden
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Forgot..
I also checked the frequency setting jumpers and they have the correct setting according to manual.
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Old 3rd January 2013, 09:13 PM   #399
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Quote:
Originally Posted by bigpandahk View Post
primary 2x115V Secondary:6V 1.25A x 2, 12V 1.25A x 2, 5V 1A x 4, 9V 1.5A x1

I use encoder for volume control
I assume those are AC not DC.
What type of encoder are you using ??

I was looking at 2 push type... one for volume control with push to mute and the second would have been source selection and on/off, however I think that would require the adruino to be on constantly and would have to figure out how to kill the display back lighting then.
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Old 3rd January 2013, 09:51 PM   #400
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Yes, those are AC.

See here INTRO H i F i D U I N O you will have most of the information.

I modified the code to include the power on/off function. DQ828 had demonstrated how to control the backlight LED Build Thread for TPA BIII + Ian Async I2S FIFO + OPC NTD1 + Salas SSLV
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