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Old 14th October 2012, 08:16 AM   #241
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What qusp said.

This is just rough psuedocode because I haven't written anything for arduino in a while so syntax is a bit hazy but you'll see where I'm going.


This will have to change if you end up going to Si570 for masterclock because MCKLx will be a set of frequencies where with the dual clock board you know the 2 freq for master clock and you know that the FIFO will be determining that based on the input sample freq.


Basically what I think what you'll have to do is in effect something like this:



Code:
int MCKL1 = 45158400;
int MCKL2 = 49152000;
int register;

[whatever code already returns register value in hifiduino]

[some code to determine if BIII is returning a rate that is a 44.1kHz multiple or if it is a multiple of 48kHz]

if (BIII register a multiple of 44.1):
     fs = register/MCKL1;
if (BIII register a multiple of 48):
    fs = register/MCKL2;

As you have noted, this change is necessary regardless of what master clock source you use, the hifiduino is written for async so there will only ever be one constant value used for master clock.

Last edited by hochopeper; 14th October 2012 at 08:24 AM.
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Old 14th October 2012, 08:31 AM   #242
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Thanks qusp and hochopeper

I can still read the register of BIII and is trying to understand how HiFiDuino calculate the magic number and divid the figure in the register by the magic number to get the frequency

hochopeper, very good point, it will be very difficult to calculate the frequency if I use the i570. May be Ian has to add output header for different frequencies
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Old 14th October 2012, 08:39 AM   #243
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Actually, the group of frequencies for ES901x DACs from the Si570 is still dual master clock, but at the faster rate. The multiplier changes to keep MCLK as detailed in this post from Ian, so you could conceivably use whatever code for the dual master clock board again for the Si570.

Quote:
Originally Posted by iancanada View Post

// Group4:Si570 frequency and *Fs combination for high mclk
{F903168, 2048*FS}, //2 44.1 KHz
{F983040, 2048*FS}, //3 48 KHz
{F903168, 1024*FS}, //4 88.2 KHz
{F983040, 1024*FS}, //5 96 KHz
{F903168, 512*FS }, //6 176.4KHz
{F983040, 512*FS }, //7 192 KHz
{F903168, 256*FS }, //8 352.8KHz
{F983040, 256*FS } //9 384 KHz
It should be possible to determine which of the above conditions is being used and apply the correct inputs to the formula to calculate and display FS.
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Old 14th October 2012, 09:31 AM   #244
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Quote:
Originally Posted by hochopeper View Post
Actually, the group of frequencies for ES901x DACs from the Si570 is still dual master clock, but at the faster rate. The multiplier changes to keep MCLK as detailed in this post from Ian, so you could conceivably use whatever code for the dual master clock board again for the Si570.



It should be possible to determine which of the above conditions is being used and apply the correct inputs to the formula to calculate and display FS.
Thanks, but it will take me sometime to understand HifiDuino's method on frequency calculation
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Old 14th October 2012, 09:54 AM   #245
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I just downloaded the hifiduino code and had a look, I think glt has used a constant depending on what asynch masterclock is on the BIII board ( 80 or 100 MHz).

You will need to set this as a variable and edit the I2S calculation inside the block of code


Code:
unsigned long sampleRate() {
//leave the code used to read registers and create 32bit number



//then change the calculation to first calculate if the DPLLnum is closer to a multiple of 44.1 or 48kHz.

//that will determine which MCLK freq the FIFO is using

//then divide by the correct number to give your fs

}

That's basically the changes I think will need to be made to that function. Since I don't have a ES901x DAC or hifiduino I'm not prepared to have a stab at the code because I can't easily test it.
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Old 14th October 2012, 12:25 PM   #246
qusp is offline qusp  Australia
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ahh yes the DPLL NUM pin/registers, but I suppose thats where the BIII onboard MCU is getting this info from and rebroadcasting it for the arduino to pick up via i2c
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Old 14th October 2012, 01:18 PM   #247
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I read the DPLLNum register during Async and Sync mode, the figure is quite stable at Async but it drifting a lot during sync mode. It is not possible to calculate it

With the default constant in glt's code, it shows 192000 at Async but showing 0, 1472, 39xxxx, 24xxxxxx, 25xxxxxx in Sync mode
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Old 14th October 2012, 01:37 PM   #248
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I believe that it should be possible to calculate it, I need to read the datasheet to give you better advice though. What I am thinking at the moment is to truncate the result from that register and then compare to a set of ranges and depending on the range it falls in it should be able to determine which fs is being used.


Also, what are the frequencies two clocks that you are using in the dual clock board at the moment?

I will dig up my copy of the datasheet tomorrow and if I have any ideas I'll let you know.
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Old 14th October 2012, 02:29 PM   #249
glt is offline glt  United States
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Quote:
Originally Posted by bigpandahk View Post
Thanks, but it will take me sometime to understand HifiDuino's method on frequency calculation
The "magic" number is just an integer value that will give the closest match to a floating point calculation. When I started doing this, I figure I would use integer operation rather than floating point because floating point operation is "slow" in the arduino.

But the "magic" number should still work with the new frequency by replacing 80000000 or 100000000 with the new master frequency from the FIFO. However, I can't think of any way to detect that the master frequency has changed unless indicated by the FIFO

But, one way you can do it locally is to determine the error in the sample rate calculation: if the error is "too large" compared to what it is expected, then you switch to the other frequency.

There is one more things: According to Dustin in this article: 6moons audio reviews: Wyred4Sound DAC2

" You can use the ASRC if you like - or not by simply clocking the XIN pin synchronously (at an integer multiple) to the BCLK. Then the ASRC drops itself out, reverting in this case to a more conventional method as the other DACs I'm aware of do."

I don't know what it means by "drops itself out", but if DAC determines that the signal is synchronous, it may choose to disable the ASRC and therefore the DPLL may be just "freewheeling" Check comment #4 in this post: Poor Man’s Jitter Measurement H i F i D U I N O

Again I don't know exactly what is "freewheeling", but it could mean the DPLL is just "going all over the place". If this is the case, then you cannot calculate the sample rate.

Thanks for sharing all the work guys :-)
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Old 14th October 2012, 02:36 PM   #250
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Quote:
Originally Posted by hochopeper View Post
I believe that it should be possible to calculate it, I need to read the datasheet to give you better advice though. What I am thinking at the moment is to truncate the result from that register and then compare to a set of ranges and depending on the range it falls in it should be able to determine which fs is being used.


Also, what are the frequencies two clocks that you are using in the dual clock board at the moment?

I will dig up my copy of the datasheet tomorrow and if I have any ideas I'll let you know.
Thanks again for your help, I am using the same frequencies as Ian, 45.1584 & 49.1520.
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