Hello all,
I am currently working on a USB DAC with PCM2707 and PCM1794 and they are connected via I2S.
I am looking at the data sheets and some designs online and I am curious about one thing... some designs include in-line resistors in the I2S signals between the chips. I tried looking as to why are people doing that and data sheets are omitting it.
I also noticed that there are in-line resistors on the USB lines at D+ and D- at 22ohms. I just put them there because that is what was show in the datasheet and other design but without really thinking about it.
So what are the reasons behind those in-line resistors on the digital lines? and how I can pick the optimal values/types of resistors and position?
I assume it has to deal with stabilizing the signal so we get cleaner/stable square waves by putting an in-line load on the digital line.
Thank you,
IT
I am currently working on a USB DAC with PCM2707 and PCM1794 and they are connected via I2S.
I am looking at the data sheets and some designs online and I am curious about one thing... some designs include in-line resistors in the I2S signals between the chips. I tried looking as to why are people doing that and data sheets are omitting it.
I also noticed that there are in-line resistors on the USB lines at D+ and D- at 22ohms. I just put them there because that is what was show in the datasheet and other design but without really thinking about it.
So what are the reasons behind those in-line resistors on the digital lines? and how I can pick the optimal values/types of resistors and position?
I assume it has to deal with stabilizing the signal so we get cleaner/stable square waves by putting an in-line load on the digital line.
Thank you,
IT
Should be placed at the source end of the I2S signal path. (Provides a terminating impedance for reflections from the driven device so they do not corrupt the transmitted signal.)
From experience they don't work too well [read as "really badly"] at the receiving end particularly if the traces/wires are a few inches long.
47 - 100 ohms work well and should be low inductance types such as smd resistors.
From experience they don't work too well [read as "really badly"] at the receiving end particularly if the traces/wires are a few inches long.
47 - 100 ohms work well and should be low inductance types such as smd resistors.
doh....
Thank you for that obvious answer..... I am stupid, should have known better
Anyways some tips on impedance matching practices would be useful
I always have a problem with impedance matching and never quite get how to calculate it and sometimes it seems as simple as just putting the same resistor values on the sending and receiving ends? but sometimes it doesn't make sense in some circuits
I am gonna have more of those problems with the amp input and output impedance... i know it :/
Thank you for that obvious answer..... I am stupid, should have known better
Anyways some tips on impedance matching practices would be useful
I always have a problem with impedance matching and never quite get how to calculate it and sometimes it seems as simple as just putting the same resistor values on the sending and receiving ends? but sometimes it doesn't make sense in some circuits
I am gonna have more of those problems with the amp input and output impedance... i know it :/
I think 47-100 is too much since the impedance of transmition line is around 50Ohm. For example,the dirving impedance of TTL is 13 Ohm, put a 37 Ohm in series will match the impedance for 50 Ohm. It's correct that the resistor should be put at the driver end.
In my opinion it's not necessary for I2S at all. Several MHz Is far from high speed digital. It really count in USB2.0 or 3.0.
In my opinion it's not necessary for I2S at all. Several MHz Is far from high speed digital. It really count in USB2.0 or 3.0.
I2S series terminate at the transmitting end ONLY. (No parallel termination at the receiving end - remember this is logic level stuff and you don't want to divide logic levels by 2..)
For general audio just remember that the load impedance should generally be >10X the driving impedance for best performance. Smaller ratios are possible with some loss of gain and potential for increases in distortion particularly at high signal levels.
Exception: Most tube power amplifiers are matched to their load and the source impedance is often rather significant relative to the loudspeaker driven particularly in the case of SE amps with no global feedback. This is often expressed as damping factor which in tube amps is often quite low frequently 10 or less.
Impedance matching works in the same way in high speed digital circuit as the audio amplifier, the only thing need to be concerned is that you must think in complex impedance instead of resistance in high speed circuit.
Thank you for that obvious answer..... I am stupid, should have known better
Anyways some tips on impedance matching practices would be useful
I always have a problem with impedance matching and never quite get how to calculate it and sometimes it seems as simple as just putting the same resistor values on the sending and receiving ends? but sometimes it doesn't make sense in some circuits
I am gonna have more of those problems with the amp input and output impedance... i know it :/
This isn't really about impedance matching. Without termination, there will be unavoidable reflections from the far end. So if it were about impedance matching there would be terminations. In digital circuits these can be done without compromising the logic thresholds too much by putting a C in series with the termination R.
Designers (myself included) use series resistors on digital lines for bandwidth limitation and hence noise mitigation.
Look at the bit clock, data and system clock for I2S with 24 bit 192kHz audio, it's not quite as trivial as you think.. SCLK in my dac runs at close to 25MHz (128FS or 24.576MHz) and the edges have rise and fall times of much less <10nS. Data is 9.216Mbits/sec, LRCLK half this..(Assuming I have done my math right.) I'm using Wolfson WM8804 and a pair of PCM1794A in mono mode and was having a lot of trouble with SCLK. (MCLK on 8804)
FWIW few dacs I have seen use controlled impedance lines for I2S, and cmos logic with low gate capacitance have high input impedances. The results of reflections may be seen. Perhaps this is less of an issue with old chips but certainly with the WM8804 the termination is important - I learned this the hard way.
Almost all high speed digital hardware (embedded systems, ATE) I have seen uses 47 ohm series terminations.. TTL/CMOS device output impedance is a function of device family - I've never seen 13 ohms quoted in any data sheet I have seen, did you measure it and if so what device(s)?
13 ohms would be fairly accurate for AC logic family standard gates running at 5V. Its not directly quoted in the datasheets but can be estimated from the output voltage vs load current graphs they show. It does depend on output logic level - in general logic 0 is sourced from a lower impedance than a logic 1, no matter what the family.
Some of the above posts are inaccurate...
We're talking about basic high speed digital design, i.e. we want the logic 0/1 to arrive at the destination (where it matters) at the right levels and at the right time.
The uni-directional (transmitter --> receiver) signal is as simple as things can get and is what I2S runs on. You worry about reflection when the wire/trace is long and/or when the signal risetime is fast (e.g. a simple reset signal from a FPGA can have issues). To help alleviate that, series termination (located at the transmittter) is the simplest form. Your PCB stackup and trace width/separation should also be design to match the impedance characteristics (e.g. 50ohms usually for single-ended, USB is 85ohms differential).
Now how do you know if your circuit is well taken care of? You look at the signals with a scope (proper probing required). You want to ensure that the signal rise/fall edges are monotonic, under/overshoot is within spec and crosstalk from adjacent signals are acceptable. The first 2 parameters are achieved by proper high speed layout techniques (use termination, proper pcb traces, minimal via transitions, no routing over plane splits, etc). The last parameter is achieved by proper pcb layer stackup design and wise routing.
Do NOT EVER put caps on digital transmission lines. Series caps are typically for AC coupling (more commonly seen with PCIe than I2S). Parallel caps can snub terminations but the danger here is that they slow down the risetime of the signal and can lead to loss of timing margin (data setup/hold).
Series termination are used successfully for far more complex stuff, e.g. SPI at 50MHz, DDR2/3 at 500MHz. Typical values are 22R-33R. I have never seen 47R series termination resistors in any embedded design. I was just at Embedded Systems Conference West in San Jose. Saw plenty of reference designs, including I2S/digital audio stuff. Nope, no 47R there.
Look up Dr Howard Johnson's books (the digital designer, not the hotel chain). Lots of good info.
For the typical hobbyist like the OP with a simple I2S circuit, I'd just put my chips as close together on the PCB as possible and call it a day. If you like to cable I2S from one board to another, then that is where you'll run into issues. Most important point for cabling I2S is to ensure adequate ground returns for every signal (e.g. you use ribbon cable, put a GND wire next to every signal, use a 2-row connector with one row being all GND pins). Consider active buffering if your cabling is long.
Hope this helps.
We're talking about basic high speed digital design, i.e. we want the logic 0/1 to arrive at the destination (where it matters) at the right levels and at the right time.
The uni-directional (transmitter --> receiver) signal is as simple as things can get and is what I2S runs on. You worry about reflection when the wire/trace is long and/or when the signal risetime is fast (e.g. a simple reset signal from a FPGA can have issues). To help alleviate that, series termination (located at the transmittter) is the simplest form. Your PCB stackup and trace width/separation should also be design to match the impedance characteristics (e.g. 50ohms usually for single-ended, USB is 85ohms differential).
Now how do you know if your circuit is well taken care of? You look at the signals with a scope (proper probing required). You want to ensure that the signal rise/fall edges are monotonic, under/overshoot is within spec and crosstalk from adjacent signals are acceptable. The first 2 parameters are achieved by proper high speed layout techniques (use termination, proper pcb traces, minimal via transitions, no routing over plane splits, etc). The last parameter is achieved by proper pcb layer stackup design and wise routing.
Do NOT EVER put caps on digital transmission lines. Series caps are typically for AC coupling (more commonly seen with PCIe than I2S). Parallel caps can snub terminations but the danger here is that they slow down the risetime of the signal and can lead to loss of timing margin (data setup/hold).
Series termination are used successfully for far more complex stuff, e.g. SPI at 50MHz, DDR2/3 at 500MHz. Typical values are 22R-33R. I have never seen 47R series termination resistors in any embedded design. I was just at Embedded Systems Conference West in San Jose. Saw plenty of reference designs, including I2S/digital audio stuff. Nope, no 47R there.
Look up Dr Howard Johnson's books (the digital designer, not the hotel chain). Lots of good info.
For the typical hobbyist like the OP with a simple I2S circuit, I'd just put my chips as close together on the PCB as possible and call it a day. If you like to cable I2S from one board to another, then that is where you'll run into issues. Most important point for cabling I2S is to ensure adequate ground returns for every signal (e.g. you use ribbon cable, put a GND wire next to every signal, use a 2-row connector with one row being all GND pins). Consider active buffering if your cabling is long.
Hope this helps.
These are series termination resistors, look at stuff by Howard Johnson and Eric Bogatin.
The value of the resistor has to be matched to the line impedance, generaly 50 ohm. The best way of doing this is a scope on the real layout of signal integrity simulation software. The impedance will only be +/- 20% unless controlled impedance PCB's are used. Values I have seen are usually between 47 and 100r when based on rules of thumb. When I get chance I have some scope shots showing the effects of resistor value on waveforms, both measured and simulated.
The value of the resistor has to be matched to the line impedance, generaly 50 ohm. The best way of doing this is a scope on the real layout of signal integrity simulation software. The impedance will only be +/- 20% unless controlled impedance PCB's are used. Values I have seen are usually between 47 and 100r when based on rules of thumb. When I get chance I have some scope shots showing the effects of resistor value on waveforms, both measured and simulated.
I guess its been a while since youve looked at digital audio signal bandwidth. clocks are pushing 100MHz with 32/384 and up to 32/768khz PCM and then we have DXD and DSD
Actually... they don't "match" nothing, they just add series resistance to the transmission line to cover the native series inductance of the traces and therfore reduce the Q of the circuit.
The traces impedance is not 50 ohm (unless you make the connections with coaxial cable).
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If constant width, then PCB traces do form a transmission line. Transmission lines do not have to be coaxial. The impedance could be 50 ohms, or less or more. Back termination (i.e. at the sending end) is a valid technique to damp reflections while maintaining full voltage swing into a mismatched (i.e. high impedance) load. In uncritical situations the match does not have to be that good, just good enough to rapidly attenuate reflections.
1. These resistors are there for transmission line impedance matching.
These
2. These resistor values should be choosen based on source impedance of drivers and transmission line impedance.
3. There are several ways of line termination - series, paralel, thevelin and it's variations, and series-paralel.
Transmission line impedance is a rate between it's inductance and capacitance to ground per length. Inductance is usually constant thing, based on length, but width of trace won't change the inductance too much. So capacitance rules the line impedance.
Capacitance is the heigh of coductor above ground plane, and conductor's area.
So, to get certain impedance, you need to control board(dielectric) thickness and trace width. Board thicknesses are a standart values, but trace width is up to your consideration.
Trace impedances wary greatly. For example, you can't really get low (50ohm) impedance on 1.6mm board. You'll need really wide trace, as the height of conductor above ground plane is too large to create largish capacitance required. There is a trick with waveguided coplanar wave transmission line design to get it right at 1.6mm board, but it requires precise track-ground fill spacing which make the required capacitance.
For the process involved in wave transmissions inside mismatched impedance systems:
1. Mathed line - the receivers get the signal as it went out of transmitter.
2. low impedance to high impedance transition: lots of reflections on receiver end.
3. High impedance to low impedance: wave fronts get lowpassed, no reflections.
The speed of circuit is not the rate of clock or whatever. The "speed" of circuit is the slew rate of signal fronts passing in the circuit, which are fully dependant on logic families and supply voltages involved. 8ns for HC, 3-4ns for AC, and much faster for ABT and other new logic families.
You can split the transmission lines into 2 groups - short and long. The length is determined by signal slew rate (time units) and travel speed of wave in transmission line (it is slower than speed of ligt, and impedance dependant).
Imagine a "rise" transition with 10%-90% time of 4ns. Multiply it by speed, and you get length of transition.
This lenght of wave is then is being compared to your actual track length.
If your track length is 1/10 of wave length, then you don't have real transmission line. Short traces won't affect much the signal.
If your transmission line is long, then you should both terminate it, and control it's impedance.
As a side note for EMC: the lower the impedance, the less noise it will create. The slower your logic gates, the slower their slew rate, and they produce less noise.
For DIYers: Slow logics = less care of transmission line impedances could be taken.
Coaxial cables - 50 or 75ohm.
Ribbon cables - 110ohm impedance in GSGSGSG structure (G=ground, S=Signal).
Use of ribbon cables with other than GSGSGSG structure is prohibited. SSSSSSSG - is worst case, and couldn't be used in DACs.
For better understanding of trace/pcb impedances - check a nice "calculator" - Saturn PCB Toolkit - http://saturnpcb.com/pcb_toolkit.htm
These
2. These resistor values should be choosen based on source impedance of drivers and transmission line impedance.
3. There are several ways of line termination - series, paralel, thevelin and it's variations, and series-paralel.
Transmission line impedance is a rate between it's inductance and capacitance to ground per length. Inductance is usually constant thing, based on length, but width of trace won't change the inductance too much. So capacitance rules the line impedance.
Capacitance is the heigh of coductor above ground plane, and conductor's area.
So, to get certain impedance, you need to control board(dielectric) thickness and trace width. Board thicknesses are a standart values, but trace width is up to your consideration.
Trace impedances wary greatly. For example, you can't really get low (50ohm) impedance on 1.6mm board. You'll need really wide trace, as the height of conductor above ground plane is too large to create largish capacitance required. There is a trick with waveguided coplanar wave transmission line design to get it right at 1.6mm board, but it requires precise track-ground fill spacing which make the required capacitance.
For the process involved in wave transmissions inside mismatched impedance systems:
1. Mathed line - the receivers get the signal as it went out of transmitter.
2. low impedance to high impedance transition: lots of reflections on receiver end.
3. High impedance to low impedance: wave fronts get lowpassed, no reflections.
The speed of circuit is not the rate of clock or whatever. The "speed" of circuit is the slew rate of signal fronts passing in the circuit, which are fully dependant on logic families and supply voltages involved. 8ns for HC, 3-4ns for AC, and much faster for ABT and other new logic families.
You can split the transmission lines into 2 groups - short and long. The length is determined by signal slew rate (time units) and travel speed of wave in transmission line (it is slower than speed of ligt, and impedance dependant).
Imagine a "rise" transition with 10%-90% time of 4ns. Multiply it by speed, and you get length of transition.
This lenght of wave is then is being compared to your actual track length.
If your track length is 1/10 of wave length, then you don't have real transmission line. Short traces won't affect much the signal.
If your transmission line is long, then you should both terminate it, and control it's impedance.
As a side note for EMC: the lower the impedance, the less noise it will create. The slower your logic gates, the slower their slew rate, and they produce less noise.
For DIYers: Slow logics = less care of transmission line impedances could be taken.
Coaxial cables - 50 or 75ohm.
Ribbon cables - 110ohm impedance in GSGSGSG structure (G=ground, S=Signal).
Use of ribbon cables with other than GSGSGSG structure is prohibited. SSSSSSSG - is worst case, and couldn't be used in DACs.
For better understanding of trace/pcb impedances - check a nice "calculator" - Saturn PCB Toolkit - http://saturnpcb.com/pcb_toolkit.htm
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IC source impedance usually is missing in datasheets. But you can calculate it yourself - usually the datasheet states the output voltage level for different (min max) load resistances. You have 2 voltages, 2 resistances. Use Ohm's law to calculate involved currents, and find the source impedance which stays constant for both cases.
s3tup said:
sure ok, but I dont think that was what was being discussed by siliconray here
siliconray said:
which is what I replied to and i think both types of speed are under consideration here these days are they not? with the advent of CPU's, DSPs and other core type processors like Rasberry Pi and Beaglebone are being involved in digital audio more and more. Projects like the i2s/spdif fifo buffer, they are involved in the one board.
thanks for the link though, this is certainly one of those areas i'm a complete know-nothing novice
Transmission rates and transmission line impedances aren't directly related.
You can pass 500MHz data with the same bandwidth as 44kHz. Use "sine" for 500MHz and fast slew rate "square" for 44kHz.
If you have lots of reflections, then these reflection could cause different troubles as "double clocking" where the clock arrives on IC input, and the reflection arrives a bit later - the IC sees two spikes, and then clocks twice. Even for 1Hz signal you will get the same double-clocking thing.
On the opposite side of slew rate sits jitter - we want to get the slew rate of clock as fast as possible, as it determines the uncertainty during signal transition from L to H or vice versa. The faster the edge will be, the less uncertainty in time we'll get. Less jitter the noise will introduce, as it is important during transition time only. Shorter transition time = better jitter.
You can pass 500MHz data with the same bandwidth as 44kHz. Use "sine" for 500MHz and fast slew rate "square" for 44kHz.
If you have lots of reflections, then these reflection could cause different troubles as "double clocking" where the clock arrives on IC input, and the reflection arrives a bit later - the IC sees two spikes, and then clocks twice. Even for 1Hz signal you will get the same double-clocking thing.
On the opposite side of slew rate sits jitter - we want to get the slew rate of clock as fast as possible, as it determines the uncertainty during signal transition from L to H or vice versa. The faster the edge will be, the less uncertainty in time we'll get. Less jitter the noise will introduce, as it is important during transition time only. Shorter transition time = better jitter.
I didnt say they were related, I only said they both apply. faster clock = less jitter seems counter-intuitive, as fast clock/slew rate will cause more ripple on the power supply/ground which given clocks (andf most other analogue mechanisms) usually have lower PSRR down low and phase noise in 1-100hz seems the most important spec. so while I understand what you are saying, I think its not that simple as one advantage may to some extent cancel the other
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