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Old 3rd May 2012, 05:26 PM   #21
marce is offline marce  United Kingdom
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Most boards I lay out are impedance matched to 50Ohm, or whatever is specified for the signal, ie USB. All critical traces are run as stripline and thus are transmission lines and the signal travels in TEM mode. It is easy to get 50OHm on a 1.6mm board, with digital you are usually going to have at least 8 layers, and on complex boards this number shoots up, as the aim is to run signals adjacent to a contigous ground plane to provide a unbroken return path for the signal.
The main factor that determines whether high speed design tecniques are required is not the ultimate clock frequency, but the rise time of the signal, and with todays chips, most designs have to be considered carefully. Older chips were more benign with slower rise times.
Whatever termination we use is selected using simulation software, this allows us to try different termination schemes with different value components, to get the required signal fidelity, the advantage of this is the the transmitter and reciever are also moddeled using IBIS files to you can match your termination to the complete line, silicon to silicon. With scope probe moddeling you can also simulate the view that will be seen on the scope for the real board.
With standard PCB's you can get 50Ohm +/-20%, with controlled impedance boards, you will pay more but get an accuracy of 5-10%, providing you get the stack up correct. Saturn PCB toolkit has a quick impedance calculator. Polar do more complex calculators that most PCB manufacturers use when manufacturing controlled impedance boards.

Last edited by marce; 3rd May 2012 at 05:33 PM.
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Old 3rd May 2012, 07:02 PM   #22
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IMO, such series resistors mostly serve to damp the ringing of the series resonant parasitic circuit formed by the PCB trace inductance and the logic input termination capacitance. Undamped, such ringing is quite apparent on digital signals viewed via oscilloscope. I've before measured peak ringing voltages higher than the logic supply voltage! These resistors also reduce the peak current demand placed on the logic supply, and thereby, logic supply noise, which has jitter related implications.
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Old 3rd May 2012, 09:17 PM   #23
DF96 is offline DF96  England
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'Damping the ringing' is simply the lumped approximation version of 'terminating the line'. Which is most appropriate depends on line length vs slew rate, but the EM wave version is always right even when it is overkill.
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Old 4th May 2012, 01:06 AM   #24
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Quote:
Originally Posted by DF96 View Post
'Damping the ringing' is simply the lumped approximation version of 'terminating the line'. Which is most appropriate depends on line length vs slew rate, but the EM wave version is always right even when it is overkill.
Yes, except that I seem to recall that the resistance needed to correctly damp the network ringing at the terminating end, which is in parallel with the input capacitance of the receiving node, is dramatically lower than the resistance needed to damp the network via a series connected resistance. Also, an impedance matched termination of a simple digital signal connection will cut the logic voltage levels in half at the receiving end, right smack in the region of qualifying as an invalid logic level. If the point to point connection (source, path, termination, signal levels) was originally designed for impedance matched transmission - which most audio DAC digital logic components and paths seem not to be - then, no problems.
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Old 4th May 2012, 01:17 AM   #25
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All the replies are great! So much knowledge from you guys, I need some time to digest hehe


Quote:
Originally Posted by siliconray View Post
I think 47-100 is too much since the impedance of transmition line is around 50Ohm. For example,the dirving impedance of TTL is 13 Ohm, put a 37 Ohm in series will match the impedance for 50 Ohm. .
How does 13Ohm come up as the driving impedance? Current vs voltage requirements of TTL?

I think this might be getting into microstrip design


Quote:
Originally Posted by kevinkr View Post
I2S series terminate at the transmitting end ONLY.

For general audio just remember that the load impedance should generally be >10X the driving impedance for best performance. Smaller ratios are possible with some loss of gain and potential for increases in distortion particularly at high signal levels.
in-line termination seems to be the consensus here for I2S and unidirectional digital signals

I am to read that as the souse impedance should be 10x greater than the load?



Quote:
Originally Posted by abraxalito View Post
Designers (myself included) use series resistors on digital lines for bandwidth limitation and hence noise mitigation.
Can you elaborate a little as in how adding resistance limits the bandwidth?


Quote:
Originally Posted by kevinkr View Post
Look at the bit clock, data and system clock for I2S with 24 bit 192kHz audio, it's not quite as trivial as you think.. SCLK in my dac runs at close to 25MHz (128FS or 24.576MHz) and the edges have rise and fall times of much less <10nS. Data is 9.216Mbits/sec, LRCLK half this..(Assuming I have done my math right.) I'm using Wolfson WM8804 and a pair of PCM1794A in mono mode and was having a lot of trouble with SCLK. (MCLK on 8804)

FWIW few dacs I have seen use controlled impedance lines for I2S, and cmos logic with low gate capacitance have high input impedances. The results of reflections may be seen. Perhaps this is less of an issue with old chips but certainly with the WM8804 the termination is important - I learned this the hard way.
What kind of trouble were you running at with SCLK? How did you mitigate? Did you use a 47Ohm Series termination in your design?


Quote:
Originally Posted by Arius View Post
Some of the above posts are inaccurate...

We're talking about basic high speed digital design, i.e. we want the logic 0/1 to arrive at the destination (where it matters) at the right levels and at the right time.

The uni-directional (transmitter --> receiver) signal is as simple as things can get and is what I2S runs on. You worry about reflection when the wire/trace is long and/or when the signal risetime is fast (e.g. a simple reset signal from a FPGA can have issues). To help alleviate that, series termination (located at the transmittter) is the simplest form. Your PCB stackup and trace width/separation should also be design to match the impedance characteristics (e.g. 50ohms usually for single-ended, USB is 85ohms differential).


Series termination are used successfully for far more complex stuff, e.g. SPI at 50MHz, DDR2/3 at 500MHz. Typical values are 22R-33R. I have never seen 47R series termination resistors in any embedded design. I was just at Embedded Systems Conference West in San Jose. Saw plenty of reference designs, including I2S/digital audio stuff. Nope, no 47R there.

Look up Dr Howard Johnson's books (the digital designer, not the hotel chain). Lots of good info.

Most important point for cabling I2S is to ensure adequate ground returns for every signal (e.g. you use ribbon cable, put a GND wire next to every signal, use a 2-row connector with one row being all GND pins). Consider active buffering if your cabling is long.

Hope this helps.
This helps a lot actually! Verry good write!
I guess microstrip design plays a big role in layout. I am not sure how that can be addressed at my level, especially with multiple layers and.... DipTrace routing software.

Using the following microstrip calculator I get hgher impedance in Z=100Ohm+. Are you talking in terms of simple resistance or impedance?

Those are some solid design tips there too. Very good references too, I will probably buy the book and I will consider going to that conference you mentioned. I have some travel budget for one of my projects, is the conference being held annually (a linik would help)?

Quote:
Originally Posted by marce View Post
These are series termination resistors, look at stuff by Howard Johnson and Eric Bogatin.
The value of the resistor has to be matched to the line impedance, generaly 50 ohm. The best way of doing this is a scope on the real layout of signal integrity simulation software. The impedance will only be +/- 20% unless controlled impedance PCB's are used. Values I have seen are usually between 47 and 100r when based on rules of thumb. When I get chance I have some scope shots showing the effects of resistor value on waveforms, both measured and simulated.
If you can get some scope and example of the PCB/trace layout that will be a real eye opener! I am sure others will want to see that too

Unfortunately I don't have a signal integrity simulation software?! I have access to Multisim/Ultiboard at work and DipTrace at home.

Quote:
Originally Posted by SoNic_real_one View Post
Actually... they don't "match" nothing, they just add series resistance to the transmission line to cover the native series inductance of the traces and therfore reduce the Q of the circuit.
The traces impedance is not 50 ohm (unless you make the connections with coaxial cable).
Yes that is what i see as well.... but that increases the trace/microstrip's impedance! How does that affect the transmission? Positive/Negative?

Quote:
Originally Posted by DF96 View Post
If constant width, then PCB traces do form a transmission line. Transmission lines do not have to be coaxial. The impedance could be 50 ohms, or less or more. Back termination (i.e. at the sending end) is a valid technique to damp reflections while maintaining full voltage swing into a mismatched (i.e. high impedance) load. In uncritical situations the match does not have to be that good, just good enough to rapidly attenuate reflections.
Yes they do and apparently to get at 50Ohm you need a 120mil thick trace lol so that's not a viable option.

How do you know/calculate/estimate how much a resistor termination will attenuate the reflections? Any design tips/references?
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Old 4th May 2012, 01:19 AM   #26
DF96 is offline DF96  England
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Back-termination avoids the problem of reducing logic voltage levels.

The two descriptions, wave and lumped, give the same answer in those situations where the lumped approximation is valid. Where they differ, the full wave version is correct. There is no situation in which the lumped one is correct but the wave one is wrong. For slow rise times (or short traces) you can treat the track as a lumped LC circuit, or even just a parallel C.
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Old 4th May 2012, 01:23 AM   #27
DF96 is offline DF96  England
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Quote:
Originally Posted by zxgravediggerxz
How do you know/calculate/estimate how much a resistor termination will attenuate the reflections?
Google transmission line reflection coefficient. I can never remember the formula so I just look it up.
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Old 4th May 2012, 01:41 AM   #28
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Quote:
Originally Posted by s3tup View Post
1. These resistors are there for transmission line impedance matching.
These
2. These resistor values should be choosen based on source impedance of drivers and transmission line impedance.
3. There are several ways of line termination - series, paralel, thevelin and it's variations, and series-paralel.

Transmission line impedance is a rate between it's inductance and capacitance to ground per length. Inductance is usually constant thing, based on length, but width of trace won't change the inductance too much. So capacitance rules the line impedan.................]
Another excellent write up! Very in-line with what I've studied in class with practical application.

Yes we do want to control the trace/line impedance and we can get that calculated but the questions that plague me now are:
How do I know what impedance should my lines be? 50Ohm is unfeasable for the most part and we are left with dealing with mismatch between the transceiver and receiver.
We can figure out our transmission line impedance and a 20mil trace gives you around Z=130 Ohm. Now how do I determine what resistor to put on my I2S transceiver in order to minimize reflections?

I am using the following devices and it doesn't mention impedance at the I2S protocol pins

PCM2707 USB DAC and src4192 192kHz Stereo Asynchronous Sample Rate Converter

SRC4192 mentions Digital Pin Input Capacitance CIN 3 pF but the PCM2707 doesnt state Digital output capacitance.
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Old 4th May 2012, 01:50 AM   #29
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Quote:
Originally Posted by marce View Post
Most boards I lay out are impedance matched to 50Ohm, or whatever is specified for the signal, ie USB. All critical traces are run as stripline and thus are transmission lines and the signal travels in TEM mode. It is easy to get 50OHm on a 1.6mm board, with digital you are usually going to have at least 8 layers ..........
That is some pretty intense design!

What get's me tho is why do you say that 50Ohm impedance is easy to achive in a 1.6mm? what is your trace width? According to one of my calculations it's 120mil...
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Old 4th May 2012, 02:00 AM   #30
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Quote:
Originally Posted by zxgravediggerxz View Post
Can you elaborate a little as in how adding resistance limits the bandwidth?
When we consider the circuit in a lumped form, it looks like an RC low-pass filter. R is in signal line, C to ground. The C in this case is the input capacitance (plus strays) of the receiver. The R is the output impedance of the driver plus the explicit series resistor added.
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