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#1 |
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diyAudio Member
Join Date: Mar 2006
Location: Cheshire
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What does this do?
Where would it be wired into a CD player? Universal 1ppm CD clock + SPDIF isolator low jitter ! | eBay
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Regards. Michael |
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#2 |
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diyAudio Member
Join Date: Jan 2008
Location: Virginia
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Bull... That is a programmable gate array, it cannot reduce the SPDIF jitter.
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#3 |
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diyAudio Member
Join Date: Apr 2003
Location: Eastern Pennsylvania
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The Xilinx FPGA may contain internal RAM configured as a FIFO buffer, enabling the complete isolation of input clock jitter by creating new and independent clock domain for the circuits which follow. It hard to say for sure simply based on the minimal description given.
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Ken |
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#4 |
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diyAudio Member
Join Date: Sep 2007
Location: Hangzhou - Marco Polo's 'most beautiful city'. 700yrs is a long time though...
Blog Entries: 64
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If it has a FIFO then it would need some kind of PLL but no sign of a VCXO on that board. There's only one osc, its not voltage controlled by the looks of it. I tend to agree with SoNic.
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When a measure becomes a target, it ceases to be a good measure. C.A.E. Goodhart |
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#5 |
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diyAudio Member
Join Date: Aug 2004
Location: Eindhoven, The Netherlands
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We have not been given a look at the bottom of correctly, there's no RAM. the pcb. Maybe there are components on that side too.
Edit: if I interpret the function block diagram of the XC9572XL corrcetly, it has no RAM. I would take it for what the title says: SPDIF isolator (I presume galvanic isolation) and low jitter clock, but no jitter-killer. Last edited by jitter; 26th April 2012 at 05:35 AM. |
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#6 |
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diyAudio Member
Join Date: Sep 2007
Location: Hangzhou - Marco Polo's 'most beautiful city'. 700yrs is a long time though...
Blog Entries: 64
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Decoupling caps maybe. Osc module? - improbable, though of course not impossible
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When a measure becomes a target, it ceases to be a good measure. C.A.E. Goodhart Last edited by abraxalito; 26th April 2012 at 05:34 AM. |
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#7 |
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diyAudio Member
Join Date: Mar 2004
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1ppm....
I'm always suspicious when offerings claim low jitter but are wawing the long term stability (=ppm) of their clocks. Audio needs low jitter, but doesn't care for frequency deviations in the long term. Good long term stability doesn't imply low jitter.
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#8 |
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diyAudio Member
Join Date: Apr 2003
Location: Eastern Pennsylvania
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With a more careful reading of the function description, it appears that the board simply re-generates a cleaner S/PDIF waveform. To do this with only digital means they would need to time-slice the input S/PDIF signal, hence, I presume, the TCXO. In any case, I think it not justified for anyone to reflexively declare that the FPGA cannot play a role in jitter reduction. They can and they do form key parts of a DPLL, for example, in commercial DAC boxes. Even of the FPGA here is not being utililzed to create a DPLL.
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Ken Last edited by Ken Newton; 26th April 2012 at 03:00 PM. |
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#9 |
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diyAudio Member
Join Date: Jul 2009
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please visit here for more information: ( written in chinese only )
CD&CD-ROMתÅÌÍâ¹Òʽ¸ß¾«¶ÈʱÖÓ°åVIISE - Create Dream |
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#10 |
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diyAudio Member
Join Date: Aug 2004
Location: Eindhoven, The Netherlands
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Unfortunately I don't read Chinese, but I'm guessing it's the same as the English text in the eBay advertisement.
Please tell us how jitter reduction is achieved. |
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