S/PDIF signal low frequency flutter/wander?

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I just built a DAC which utilizes the CS8416 DIR and the CS2300 jitter supression chip. The CS2300 is essentially a FIFO DPLL which features very good jitter filtering of the incoming clock. I was probing various nodes on the PCB with my Tek scope when I decided to look at the output of the CS2300. The regenerated clock there was well shaped and low in visible noise. Then I put a second probe on the input to the CS2300. With the scope triggering on the de-jittered output clock, the input clock appeared to be wandering around at a very low frequency - between about 1 to 5 Hertz. This could also be described as a randomly 'fluttering' along the time axis, and appears to be quite large in magnitude. I'd estimate the flutter/wander as varying from about 25%, up to near 50% of the clock period, peak-peak.

I probed the S/PDIF signal itself, directly at the input to the DAC, and it too exhibits the low frequency fluttering along the time axis. Needless to say, I was alarmed, and at first thought the S/PDIF output of the DVD player I was using as a CD transport was defective. I then swapped the DVD player for an old Marantz CD63SE CD player which I had my basement, but there was no apparent difference in the signal wander/flutter. The DAC locks reliably to the S/PDIF signal of either player, and plays music with no obvious degradation. Does anyone know whether such very low frequency flutter/wander is typical in an S/PDIF signal?
 
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In the second case where you probed the SPDIF input to the DAC, were you still triggering on the de-jittered output from the CS2300? If so then I think what's wandering is the CS2300's output, not the input signal.

Yes, I was still triggering on the CS2300 output. I too, include the CS2300 as among the suspects since this is my first experience with it. I arbitrairly assign it lower probability, mostly because it features such a simple implementation. Essentially, it only requires a clean power supply, which my scope verifies. But, who knows? Perhaps, I'll try adding additional bypass capacitance across the CS2300 and see if that makes any difference.
 
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Having had a quick look at the CS2300-OTP datasheet it struck me that many of the jitter figures don't seem to go down very low in frequency. The notes to the table on page 7 say the 150pS RMS figure (for example) is taken with a 100Hz high pass filter. This leaves rather open what happens below 100Hz doesn't it? :p
 
The CS2300's recomended locked PLL loop bandwidth is 128Hz. None of the digital receiver's PLL loops or other clock generators fare well below 100Hz.
You need a dual-port buffer memory at DAC input to get below that, a PLL loop with lower time constant doesn't work well (explained why in datsheet also).
 
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Having had a quick look at the CS2300-OTP datasheet it struck me that many of the jitter figures don't seem to go down very low in frequency. The notes to the table on page 7 say the 150pS RMS figure (for example) is taken with a 100Hz high pass filter. This leaves rather open what happens below 100Hz doesn't it? :p

Here's the datasheet for the CS2300-01 version which I'm using. http://www.cirrus.com/en/pubs/manual/CS2300-01_PS_A4.pdf

It is pre-configured at the factory for a 1Hz jitter filtering corner frequency, supposedly suppressing incoming jitter by about 35dB @ 100Hz (per figure 3 of the CS2300-OTP datasheet). The intrinsic baseband (100Hz to 40kHz) jitter is specified as 50ps. Although, the datasheets make to mention of intrinsic jitter below 100Hz, I can't believe it is on the order of 1000x the 50ps. spec at 100Hz, which is what I appear to to be seeing.
 
The CS2300's recomended locked PLL loop bandwidth is 128Hz. None of the digital receiver's PLL loops or other clock generators fare well below 100Hz.
You need a dual-port buffer memory at DAC input to get below that, a PLL loop with lower time constant doesn't work well (explained why in datsheet also).

This is an interesting thought. Perhaps, the incoming S/PDIF signal simply contains too much jitter for stable use with a 1Hz PLL corner, despite the signal lock appearing to be stable. I'll have to investigate further.
 
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