My NOS AD1865 DAC

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I have just finished my NOS AD1865 DAC with AudioNote like Digital Stage, 7 Salas shunt regulators, and Pass D1 IV Stage. It seems to be working and sounding fine I'm just worried exposing my amp to the HF noise from digital stair steps I don't think that the 1st order low pass filter is enough. I also can hear some fuzz from the DAC when the volume in iTunes down a lot I think that is the images from the sampling frequency. the fuzz changes on different songs. I was thinking of implementing a notch filter to remove the 44.1Khz frequency and a LC resonant filter to compensate for the sin(x)/x rolloff from the DAC. Do you think that this amount of filtering is necessary or will the phase shift it causes degrade the sound quality? I simulated it in ltspice and it seems to work in the sim. I uploaded pic's of the sim and the DAC. I could use some help getting the values of the filters right, i'm not an expert on filters.
(In the circuit the 2N7002 should be an ZVN2106A in real life.)
 

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One problem with LTSpice sims with inductors is that real world components have frequency dependent losses (proximity effect mostly, skin effect sometimes) which the software doesn't model. I see you have fairly high values (4.7mH and 10mH) which will almost certainly be multi-layer in construction. Multi-layer coils are very difficult to model accurately.

If you look at my blog I have another way to implement sin(x)/x correction - in your case you'd need to piggy back another two AD1865s and add some shift registers. It requires a DAC with fairly high output compliance to work though because the AD1965 has no reference input - do you know the output compliance? By output compliance I mean what voltage swing will the current outputs tolerate?
 
I actually think I don't need a sin filter as the HF loss is very small. I don't even think it needs anymore filtering. I love the sound of it just as it is. I just need to know if the digital stair steps could upset my amp. (cause any oscillation) its a DX Precision I from the diyaudio forum.
 
I have been messing around with spice and i found putting cap's in the spots in the the picture bellow make the frequency response peak at 20khz like the inductor circuit I soldered the parts on my pcb and i'm listening to it as a write this and it gives the highs that extra "sparkle" it was missing. but on the oscilloscope any square waves i generate with audacity have a lot of overshoot and undershoot. they didn't look like this before i added this filter. I just want to know if this type of filter is "proper" I don't even understand how its making a peak from putting them in that spot. :confused:
 

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I loved the sound of my NOS DAC without the response flattening. But I have to say that with it, its even better - more dynamic sounding than before. And it was amazingly dynamic compared to S-D DACs prior to that.

My subjective reaction to NOS response EQ is essentially the same as abraxilito's, although I use an LC tank EQ circuit constructed of film & foil (not metalized) capacitors and amorphous core inductors. The reason I believe the benefits of such EQ are readily audible is because NOS response droop broadly affects the upper audio band, bout two octaves worth, from 5kHz-20kHz. Inverse sinx/x EQ is just as broad in correcting those two octaves, not just the famous -3dB@20kHz.:)

Regarding, the output compliance of the AD1865. I've utilized passive I/V resistor values as high as 330 ohms on the AD1865 without perceptible distortion. Which equates to an output pin voltage compliance of at least 330mV peak.
 
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The reason I believe the benefits of such EQ are readily audible is because it broadly corrects the upper audio band, over about two octaves from 5kHz-20kHz, not merely 3dB@20kHz.:)

Yep, concur - I'm of the view its more the making up of the energy loss between 5k - 15k which is achieving the difference for me. My own correction doesn't manage to add 3.2dB @ 20kHz anyway.
 
I'm thinking of making a new digital PCB so I can try the SM5842 digital filter. I need to know how to interface the CS8414 to the SM5842 to the AD1865. I do not know what pins to pull high and low to get the chips to work together, could someone please help me with this step. Also I see the SM5842 needs 60ma of current my current post-regulators on the PCB can only source 30ma (TL431).
I have 3 Salas shunt regs that make 6.2V for Digital and +/- 6.2V for Analog, they connect to 6 TL431 regulators on the digital board to drop the 6.2V to 5.00V for the CS8414, etc. since I cannot use these shunt regulators anymore with the newly required high current. what would be the best method of dropping the 6.2V to 5.0V could I use one of the Linear Tech's LDO reg's or would that degrade the SQ, etc.?

I have uploaded the circuit diagram that I hooked up, I just need someone to look it over, Thanks.
 

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Why the beads on I output (with no capacitors)?

Also, I stronlgy suggest that the DGND associated with the DAC cip should be connected together with AGND at the DAC, not back to the digital part. You just injected digital noise into analog ground. That's a begginer mistake!
See page 7 from this AD tutorial:
http://www.analog.com/static/imported-files/tutorials/MT-031.pdf
...However, in order to prevent further coupling, the AGND and DGND pins should be joined together externally to the analog ground plane with minimum lead lengths. Any extra impedance in the DGND connection will cause more digital noise to be developed at point B; it will, in turn, couple more digital noise into the analog circuit through the stray capacitance. Note that connecting DGND to the digital ground plane applies VNOISE across the AGND and DGND pins and invites disaster!
The name "DGND" on an IC tells us that this pin connects to the digital ground of the IC. This does not imply that this pin must be connected to the digital ground of the system.
 
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So I should connect the AGND and DGND and coupling capacitors of the CS8414 to DGND and the AGND and DGND and coupling capacitors of the AD1865 to AGND? Should the AD1865's Digital Supply Regulators ground connect to A-GND or D-GND? Are to pins selected on the SM5842 and CS8414 connected right to make the chips interface properly?
 
The positive digital supply of AD1865 should be separated from the rest of digital circuites since it is using the analog ground. It's regulator and decoupling capacitors obvious needs to be on the same analog ground.
AD says that it can also be derived from the analog supply with a ferrite bead.
As for using the Salas shunts to feed the other regulators, I think is a total waste. Just go straight into the regs...

What's up with the title (My NOS AD1865 DAC)? The filter used (SM5842) is 8x OS, it deserves a dedicated thread.
 
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So I should connect the AGND and DGND and coupling capacitors of the CS8414 to DGND and the AGND and DGND and coupling capacitors of the AD1865 to AGND? Should the AD1865's Digital Supply Regulators ground connect to A-GND or D-GND? Are to pins selected on the SM5842 and CS8414 connected right to make the chips interface properly?
 
Thanks so much for your help, I read through the AD data sheet and I'm going to try a ground plane design. I'm just worried that it won't transfer to the PCB (I use the toner transfer method to etch boards). I drew up a new PCB file using a separate ground plane for Analog and Digital connected together at single point between the AD1865's A and D ground. Are my chips in the circuit interfacing correctly I read the data sheets and selected 18bit on the CS8414, 18bit in and 18bit out on SM5842 and clock set to 256fs. Does the SM5842 need a master clock? or does it get that from the CS8414 MCK output?

DATASHEETS:

AD1865 http://www.analog.com/static/imported-files/data_sheets/AD1865.pdf
CS8414 http://www.jitter.de/pdfextern/8413-4.pdf
SM5842 http://www.dddac.de/files/SM5842.pdf
 

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The clock is the MCK because you need to be locked into the digital data stream.
To separate the clock domains you would need either some form of ASRC (not so transparent IMO) or a generous FIFO buffer (like one of the projects here).
As for the bit depth, I think that the AD1865 will ignore what is more than 18 bit, so the devices ahead could worn on higher depth. That would allow the use of dither function in the SM5842.
I would sdd some dip-switches or jumpers (PC-style) for testing of various combinations.

For grounding I made some more suggestions. With dotted yellow I am showing the virtual boundary between the digital GND and analog GND (they need to be tied together just in that place).
Notice that the regulator gnd for the DAC is tied into the analog part too. Change it to AGND on your schematic! Also, a more direct/thick path from the DAC pin 13 to that regulator GND tab is needed, I couldn't draw it as I wanted.
Flooded ground idea might work better, even if takes a lot of tonner.
 

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