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Old 20th April 2012, 08:57 PM   #11
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I drew up a new PCB the new Digital Board comments would be appreciated.
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Old 20th April 2012, 10:06 PM   #12
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Why the beads on I output (with no capacitors)?

Also, I stronlgy suggest that the DGND associated with the DAC cip should be connected together with AGND at the DAC, not back to the digital part. You just injected digital noise into analog ground. That's a begginer mistake!
See page 7 from this AD tutorial:
http://www.analog.com/static/importe...als/MT-031.pdf
Quote:
...However, in order to prevent further coupling, the AGND and DGND pins should be joined together externally to the analog ground plane with minimum lead lengths. Any extra impedance in the DGND connection will cause more digital noise to be developed at point B; it will, in turn, couple more digital noise into the analog circuit through the stray capacitance. Note that connecting DGND to the digital ground plane applies VNOISE across the AGND and DGND pins and invites disaster!
The name "DGND" on an IC tells us that this pin connects to the digital ground of the IC. This does not imply that this pin must be connected to the digital ground of the system.

Last edited by SoNic_real_one; 20th April 2012 at 10:15 PM.
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Old 20th April 2012, 10:36 PM   #13
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So I should connect the AGND and DGND and coupling capacitors of the CS8414 to DGND and the AGND and DGND and coupling capacitors of the AD1865 to AGND? Should the AD1865's Digital Supply Regulators ground connect to A-GND or D-GND? Are to pins selected on the SM5842 and CS8414 connected right to make the chips interface properly?
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Old 21st April 2012, 12:01 AM   #14
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The positive digital supply of AD1865 should be separated from the rest of digital circuites since it is using the analog ground. It's regulator and decoupling capacitors obvious needs to be on the same analog ground.
AD says that it can also be derived from the analog supply with a ferrite bead.
As for using the Salas shunts to feed the other regulators, I think is a total waste. Just go straight into the regs...

What's up with the title (My NOS AD1865 DAC)? The filter used (SM5842) is 8x OS, it deserves a dedicated thread.

Last edited by SoNic_real_one; 21st April 2012 at 12:20 AM.
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Old 21st April 2012, 12:51 AM   #15
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So I should connect the AGND and DGND and coupling capacitors of the CS8414 to DGND and the AGND and DGND and coupling capacitors of the AD1865 to AGND? Should the AD1865's Digital Supply Regulators ground connect to A-GND or D-GND? Are to pins selected on the SM5842 and CS8414 connected right to make the chips interface properly?
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Old 21st April 2012, 04:01 AM   #16
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Its' 11:59PM, but I'll try a quick scketch. Hope you get the ideea...
Look at AD document too.
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Last edited by SoNic_real_one; 21st April 2012 at 04:06 AM.
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Old 21st April 2012, 02:20 PM   #17
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Thanks so much for your help, I read through the AD data sheet and I'm going to try a ground plane design. I'm just worried that it won't transfer to the PCB (I use the toner transfer method to etch boards). I drew up a new PCB file using a separate ground plane for Analog and Digital connected together at single point between the AD1865's A and D ground. Are my chips in the circuit interfacing correctly I read the data sheets and selected 18bit on the CS8414, 18bit in and 18bit out on SM5842 and clock set to 256fs. Does the SM5842 need a master clock? or does it get that from the CS8414 MCK output?

DATASHEETS:

AD1865 http://www.analog.com/static/importe...ets/AD1865.pdf
CS8414 http://www.jitter.de/pdfextern/8413-4.pdf
SM5842 http://www.dddac.de/files/SM5842.pdf
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Last edited by benproiii; 21st April 2012 at 02:23 PM.
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Old 21st April 2012, 04:13 PM   #18
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The clock is the MCK because you need to be locked into the digital data stream.
To separate the clock domains you would need either some form of ASRC (not so transparent IMO) or a generous FIFO buffer (like one of the projects here).
As for the bit depth, I think that the AD1865 will ignore what is more than 18 bit, so the devices ahead could worn on higher depth. That would allow the use of dither function in the SM5842.
I would sdd some dip-switches or jumpers (PC-style) for testing of various combinations.

For grounding I made some more suggestions. With dotted yellow I am showing the virtual boundary between the digital GND and analog GND (they need to be tied together just in that place).
Notice that the regulator gnd for the DAC is tied into the analog part too. Change it to AGND on your schematic! Also, a more direct/thick path from the DAC pin 13 to that regulator GND tab is needed, I couldn't draw it as I wanted.
Flooded ground idea might work better, even if takes a lot of tonner.
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Last edited by SoNic_real_one; 21st April 2012 at 04:35 PM.
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Old 21st April 2012, 04:20 PM   #19
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So the circuit the way it is will not work without a external clock?
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Old 21st April 2012, 04:32 PM   #20
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Yes it works. The external clock is the one embedded in SPDIF, extracted and put to MCK.
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