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Old 12th March 2012, 09:12 PM   #11
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I powered 74HC04N +5VDC pin 14 & GND pin 7, used pins 13/in & 12/out and pins 1/in & pin 2/out, it's OK?
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Old 12th March 2012, 09:21 PM   #12
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Quote:
Originally Posted by Ken Newton View Post
If k'm not mistaken, Thorsten Loesch doesn't much care for this type of circuit utilized at the S/PDIF input. I seem to recall him writing about how the fact that the output being coupled back to the input sends interference back up the S/PDIF line.

Have you tested it for lock robustness without the logic inverters in circuit?
Yes in BIII to setting the DPLL bandwith I used SW1 pins 5,6 & 7 ON position that's the highest setting this value will allow the DAC to get a lock to the incoming signal much easier, but at the same time it will allow more jitter to pass through but still have dropouts, tonight I will try default setting SW1 pins 5,6 & 7 OFF position, In ‘Default’ mode the DAC attempts to set the DPLL bandwidth automaticly. I will tell you how this setting goes.
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Old 13th March 2012, 08:35 AM   #13
JensH is offline JensH  Denmark
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@Ken
It does look more complicated than what is needed, but if it's what merlin el mango wants to try that's fine with me.

@ merlin el mango
The supply voltage for the buffered and un-buffered '04 may be the same, but that does not mean that their performance will be the same. The buffered version is not very good in this kind of circuit with an analog feedback. It could easily become unstable.

One thing that just struck me is that you might need to add a decoupling capacitor on the 5V supply, e.g. a 100nF ceramic capacitor with leads as short as possible. Such a capacitor is not shown on your schematic and it is not visible on the PCB either, but it could of course be hidden on the backside. If there is no decoupling capacitor you definitely need to add one. If there is no supply decoupling and you even use a buffered '04 there is a very high risk of instability, so perhaps you have got a signal on the output at several MHz?
If you need a TTL level input for the Buffalo I assume you actually only need one output.
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Old 13th March 2012, 12:49 PM   #14
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Quote:
Originally Posted by JensH View Post
@Ken
It does look more complicated than what is needed, but if it's what merlin el mango wants to try that's fine with me. Could you post other less complicated schematic to buffer the input S/PDIF or better to avoid jitter?

@ merlin el mango
The supply voltage for the buffered and un-buffered '04 may be the same, but that does not mean that their performance will be the same. The buffered version is not very good in this kind of circuit with an analog feedback. It could easily become unstable. OK I understand, but the question is: I need to buffer the S/PDIF or I ned to reduce the jitter, I mind that I need to reduce jitter, if so wich schematic can I to implement?

One thing that just struck me is that you might need to add a decoupling capacitor on the 5V supply, e.g. a 100nF ceramic capacitor with leads as short as possible. Such a capacitor is not shown on your schematic and it is not visible on the PCB either, but it could of course be hidden on the backside. If there is no decoupling capacitor you definitely need to add one. If there is no supply decoupling and you even use a buffered '04 there is a very high risk of instability, so perhaps you have got a signal on the output at several MHz? OK I solder 100nF directly at the Vcc & Gnd of 74HC04N
If you need a TTL level input for the Buffalo I assume you actually only need one output. Yes I need only one output
Answer in red.

Thanks for help.
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Old 13th March 2012, 01:27 PM   #15
JensH is offline JensH  Denmark
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A way to modify it could be as follows:

Short circuit R2.
Change R3 to 300ohm (I assume here that the impedances are optimized for use with this transformer).
Take the output from R9.

You can of course also remove C1, R4, R6 and R8 if you like, but it is not absolutely necessary, at least for a quick test.

See also: S/PDIF Digital to Analogue Converter

If the Buffalo III expects a 3V logic level perhaps you should also try to reduce the supply voltage from 5V to 3V or 3.3V

The proposed modification also has the advantage that you get twice as much signal available. This may in fact reduce the jitter to some degree. But the circuit will not really reduce the jitter. The best you can hope for is that the circuit will not add too much jitter. If you want to reduce the jitter you will need a receiver with a PLL or something similar, e.g. a Wolfson SPDIF receiver, but then it is of course a much more complicated design.
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Old 13th March 2012, 02:49 PM   #16
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Quote:
Originally Posted by merlin el mago View Post
This buffered SPDIF input stage designed by Jocko Homo can avoid dropouts in my Buffalo III?

Rz 100R
R1 300R
Cz 4,7pF/5pF

Hex Inverter used Phillips 74HC04N instead of 74HCU04, operating voltage between +5V

Is there is a way to improve the schematic or needs other operating voltage, suggestions will welcome.

Hello
The output signal is inverted or not with this stage ?
Serge
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Old 13th March 2012, 03:02 PM   #17
JensH is offline JensH  Denmark
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The polarity of an SPDIF signal doesn't matter.
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Old 13th March 2012, 04:19 PM   #18
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The project become more complicated because BIII needs for consumer level S/PDIF a comparator or other type of conversion. Also my BIII have soldered the jumpers for S/PDIF-4 input board & Sidecar.

Anyway thanks for help.
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Old 13th March 2012, 04:32 PM   #19
zinsula is offline zinsula  Switzerland
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This circuit has been proposed by Jocko Homo for the CS8412 / ..14 receiver chips, which have schmitt trigger inputs. Those schmitt trigger inputs can send back garbage, and the chip "liked" to be driven differentially.
Maybe you should check first what the ESS chip really likes to see at the input, and if there is a +RX and -RX pin for diff input. It could well be better to use a fast (video) opamp instead of the inverter.
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Old 13th March 2012, 05:37 PM   #20
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Quote:
Originally Posted by zinsula View Post
This circuit has been proposed by Jocko Homo for the CS8412 / ..14 receiver chips, which have schmitt trigger inputs. Those schmitt trigger inputs can send back garbage, and the chip "liked" to be driven differentially.
Maybe you should check first what the ESS chip really likes to see at the input, and if there is a +RX and -RX pin for diff input. It could well be better to use a fast (video) opamp instead of the inverter.
Yes you have reason, I'm going in other direction: jitter reduction because I have TP S/PDIF-4 Input board for BIII & still I have dropouts
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