Yep, that's one of its key features - the ability to drive the poweramp directly. The volume control I'm using is an Analog Devices analog DC-controlled attenuation part - so no contacts, no switches and definitely no VCAs
Hi,
Yes, that is an interesting part, but it most definitly does have switches, Fet ones at that and under conditions where they are exposed to some serious current.
Still, I'll have to get me some and try them.
I like the combination of analog volume, low-Z in GM stage (open loop it would seem) and TI output. Oh and let's not forget, massive bandwidth which puts the video Op-Amp's I played with in the last millenium to shame. Might be fun.
Shame it does not glow nicely, at least not very long...
Ciao T
Yep, that's one of its key features - the ability to drive the poweramp directly. The volume control I'm using is an Analog Devices analog DC-controlled attenuation part - so no contacts, no switches and definitely no VCAs
Yes, that is an interesting part, but it most definitly does have switches, Fet ones at that and under conditions where they are exposed to some serious current.
Still, I'll have to get me some and try them.
I like the combination of analog volume, low-Z in GM stage (open loop it would seem) and TI output. Oh and let's not forget, massive bandwidth which puts the video Op-Amp's I played with in the last millenium to shame. Might be fun.
Shame it does not glow nicely, at least not very long...
Ciao T
Veroboard TDA1541 Part 2
Folks,
A while earlier before various little waterglass stromes we were discussing the "easy way" to make a decent DIY DAC with TDA1541, without recourse to hacking up kits and with better resulting better performance.
Part 1 discussing the general circuit is here:
http://www.diyaudio.com/forums/digital-line-level/203511-any-good-tda1541a-dac-kit.html#post2854098
Incidentally, if anyone fancies making a drawing of the circuit discussed I will not object... I lack the time.
The next step is lay out your vero board.
I find it usefull to get either the real parts, or paper cut-outs to serve as stand-ins and to push them around until I get physical relationships that please my sense of symmetry but more crucially minimise relevant (AC) current loops.
And remember PCB's have two sides and often the shortest way to connect two points on top of a PCB with a capacitor is to have the capacitor on the bottom.
Also remember, with prototyping boards we are not limited to using PCB traces - no-one is stopping us running wires or even isolated copper tape over ground-planes to create structures that would as a real PCB need at least four layers, possibly six. Think about playing startreck 3D chess for a bit to get the "flat world" perspective out of your system.
A particular tick I like is to "bridge over" the power lines using an axial choke (looks like a resistor, mostly), spaced above the board using ferrite beads, with each spacer/bead being one of two formulations , the choke itself usually looses it at a few MHz at best, a "low RF" ferrite bead then takes over and as this looses effectiveness a "high RF" ferrite bead (like >100R @ 100MHz) takes over. Any shunt element are on the "far side"of this arrangement.
Guido Tent's document on decoupling contains all we will need for this build, all shunt elements (capacitors, regulators - for AC even series regulators are actually shunts) need to offer a minimal loop area. Modern IC's often have adjecent ground and power pins ideally spaced for 0603 or 0402 capacitors. See the CS8414 photos earlier in the thread for an example - the 0603 size SMD cap's are 1uF, the 1206 size SMD cap's are 10uF.
For those to whom 0603 or 1206 may as well be chinese, these sizes in inch of the capacitor/resistor etc. So 0603 means a part that 0.06 of an inch long and 0.03 of an inch wide. When buying these I tend to buy at least 10 times what I need as soldering them by hand under aggravated circumstances means I loose more than I solder, many more.
Alas, all the chip's in our "DAC requiring I2S source" build are DIP and laid out in ways that are very un-modern and at best force very long loop areas. It cannot be helped, but emphasises even more the need to get the layout right.
So there is little point bothering with 0603 parts or even X2Y ones. John Brown's use of Picogates is definitly the way to go, especially with 4 layer PCB's and 3D Layout, but I can barely see them things and I refuse to hand-solder them (I absolutely draw the line at 0603).
There is a price to pay for using DIY friendly methods. But given what the "commercial competition" turns out we are quite safe even with these old methods.
An important consideration is always "where does the current flow"?
For example, the I2S attenuators draw current from the driving IC.
By making the reclocker IC a 74HC175 Quad Flip-Flop and loading both outputs of each flip-flop equally we avoid most of the problems modulating the powersupply, but the current will still show glitches and it wants to return to the ground pin of the 74HC175, NOT to the TDA1541... So make your arrangements accordingly.
On the other hand, the TDA1541 inputs draw VERY little current, so we can connect them from the I2S attenuators with fairly long and fairly thin wires (don't overdo it to prove a point though).
This very simple and strait forward rule of "current flows in loops and and long loops mean trouble" is missed by many.
As it stands using 1206 SMD parts for the 74HC logic in DIP format (that is parts with pins that go through the board, not SMD) will do.
For the TDA1541 use the same SMD Film Cap's for both decoupling the DEM Pins (14pcs in total) and to decouple the supply pins (3).
Using 0.1uF Panasonic types in 1210 format (stand them on edge to fit) means they are effective to around 12MHz. As the TDA1541 is bipolar current steering based, it does behave rather different from modern CMOS chips in terms of PSU noise and has no real problems with this kind of decoupling, a CMOS chip on the other hand would be a disaster area decoupled like this.
For the TDA1541 all the decoupling capacitors should be placed below the Chip pointing inwards, with a solid ground plane under the chip. Philips has this implemented in some models, but with very poor quality capacitors and a "ground-plane" that looks more like a knitting project:
image Courtesy of Lampizator
Translate this arrangement to a solid copper foil ground plane and using SMD Film Cap's soldered directly to the TDA1541 Pins and you are already miles better than anything else out there with TDA1541, save a few very select exceptions. The same idea mostly works for the rest of the logic.
All of this brings us to the ground-plane. Now vero-boards don't have one.
But you can very nice copper foil that is much thicker than what is found on most PCB's and is rolled from solid oxygen free copper instead of being electron deposited on some plastic at arts and craft shops as well at some electronic supply houses.
Above we where experimenting with layouts using vero-board and real parts or paper cutouts to find arrangements that work, now use paper cutouts to work up a ground plane arrangement that leaves all the pins we need to access at least one pad space and at the time links all grounds with as low an impedance (short distance, wide track) as possible.
Once you worked it out in paper (several times if needed), cut two copies out of the copper-foil using an exacto mini knife, with all the sections removed where we need no shorts.
The way this can look is shown by Naim in this Image:
image Courtesy of Lampizator
The arrangement of the decoupling capacitors however is way suboptimal, avoid copying this, after all, we want high performance here!
Next, attaching your copper foil ground-plane to vero-board.
You need to tin one side of the copper foil, if the vero-bard is not pre-tinned (nowadays they are often gold-flashed) tin all the pads/vias the copper foil is going to cover as well, except those that will later hold IC pins (yes, planning is definitely required).
Paste you copper-foil on top, start by heating your copper-foil with a big soldering iron in corner, so you can make sure it positioned perfectly and if needed slightly shift it to fit. If you get this wrong you will be needing new vero-board and copper-foil, BTW.
Okay, now we solder the whole surface of the copper foil to the vero-board, which will incidentally also tin the surface and stop it oxidising. do not solder where IC Groound pins will be, we solder that later.
Did I mention using brasso to clean the foil super shiny? - probably not, well do it before you cut and use cotton gloves handling the foil, or not, depending how neurotic you are.
Having pasted one side of the foil use a sowing needle (and thimble) to punch the holes where the future IC (ground) Pins will go. Hopefully you did not solder them, otherwise you might as well re-drill them. Repeat for the other side.
Fit the IC's, decoupling cap's etc. and then run the needed wires and foils for signals and supplies.
If you spend some time and effort on this you will have a result that most 4-Layer PCB's cannot match, in terms of optimum current loops and ground impedance.
Of course, you can also integrate your oscillators (whatever takes your fancy) and other parts to implement whatever interface you like and with isolation in the same manner, many of the parts needed for this are still available in DIP format and while this is by far from optimum, you can easily do better with well implemented DIP parts than most get with badly implemented SMD parts.
Or you can buy one of John Browne's DAC's or if you are more a BIY than DIY type and all of this is a bit much, audition some decent commercial implementations and buy the one that combines affordability (to you) with good sonics (to you)...
Ciao T
Folks,
A while earlier before various little waterglass stromes we were discussing the "easy way" to make a decent DIY DAC with TDA1541, without recourse to hacking up kits and with better resulting better performance.
Part 1 discussing the general circuit is here:
http://www.diyaudio.com/forums/digital-line-level/203511-any-good-tda1541a-dac-kit.html#post2854098
Incidentally, if anyone fancies making a drawing of the circuit discussed I will not object... I lack the time.
The next step is lay out your vero board.
I find it usefull to get either the real parts, or paper cut-outs to serve as stand-ins and to push them around until I get physical relationships that please my sense of symmetry but more crucially minimise relevant (AC) current loops.
And remember PCB's have two sides and often the shortest way to connect two points on top of a PCB with a capacitor is to have the capacitor on the bottom.
Also remember, with prototyping boards we are not limited to using PCB traces - no-one is stopping us running wires or even isolated copper tape over ground-planes to create structures that would as a real PCB need at least four layers, possibly six. Think about playing startreck 3D chess for a bit to get the "flat world" perspective out of your system.
A particular tick I like is to "bridge over" the power lines using an axial choke (looks like a resistor, mostly), spaced above the board using ferrite beads, with each spacer/bead being one of two formulations , the choke itself usually looses it at a few MHz at best, a "low RF" ferrite bead then takes over and as this looses effectiveness a "high RF" ferrite bead (like >100R @ 100MHz) takes over. Any shunt element are on the "far side"of this arrangement.
Guido Tent's document on decoupling contains all we will need for this build, all shunt elements (capacitors, regulators - for AC even series regulators are actually shunts) need to offer a minimal loop area. Modern IC's often have adjecent ground and power pins ideally spaced for 0603 or 0402 capacitors. See the CS8414 photos earlier in the thread for an example - the 0603 size SMD cap's are 1uF, the 1206 size SMD cap's are 10uF.
For those to whom 0603 or 1206 may as well be chinese, these sizes in inch of the capacitor/resistor etc. So 0603 means a part that 0.06 of an inch long and 0.03 of an inch wide. When buying these I tend to buy at least 10 times what I need as soldering them by hand under aggravated circumstances means I loose more than I solder, many more.
Alas, all the chip's in our "DAC requiring I2S source" build are DIP and laid out in ways that are very un-modern and at best force very long loop areas. It cannot be helped, but emphasises even more the need to get the layout right.
So there is little point bothering with 0603 parts or even X2Y ones. John Brown's use of Picogates is definitly the way to go, especially with 4 layer PCB's and 3D Layout, but I can barely see them things and I refuse to hand-solder them (I absolutely draw the line at 0603).
There is a price to pay for using DIY friendly methods. But given what the "commercial competition" turns out we are quite safe even with these old methods.
An important consideration is always "where does the current flow"?
For example, the I2S attenuators draw current from the driving IC.
By making the reclocker IC a 74HC175 Quad Flip-Flop and loading both outputs of each flip-flop equally we avoid most of the problems modulating the powersupply, but the current will still show glitches and it wants to return to the ground pin of the 74HC175, NOT to the TDA1541... So make your arrangements accordingly.
On the other hand, the TDA1541 inputs draw VERY little current, so we can connect them from the I2S attenuators with fairly long and fairly thin wires (don't overdo it to prove a point though).
This very simple and strait forward rule of "current flows in loops and and long loops mean trouble" is missed by many.
As it stands using 1206 SMD parts for the 74HC logic in DIP format (that is parts with pins that go through the board, not SMD) will do.
For the TDA1541 use the same SMD Film Cap's for both decoupling the DEM Pins (14pcs in total) and to decouple the supply pins (3).
Using 0.1uF Panasonic types in 1210 format (stand them on edge to fit) means they are effective to around 12MHz. As the TDA1541 is bipolar current steering based, it does behave rather different from modern CMOS chips in terms of PSU noise and has no real problems with this kind of decoupling, a CMOS chip on the other hand would be a disaster area decoupled like this.
For the TDA1541 all the decoupling capacitors should be placed below the Chip pointing inwards, with a solid ground plane under the chip. Philips has this implemented in some models, but with very poor quality capacitors and a "ground-plane" that looks more like a knitting project:
image Courtesy of Lampizator
Translate this arrangement to a solid copper foil ground plane and using SMD Film Cap's soldered directly to the TDA1541 Pins and you are already miles better than anything else out there with TDA1541, save a few very select exceptions. The same idea mostly works for the rest of the logic.
All of this brings us to the ground-plane. Now vero-boards don't have one.
But you can very nice copper foil that is much thicker than what is found on most PCB's and is rolled from solid oxygen free copper instead of being electron deposited on some plastic at arts and craft shops as well at some electronic supply houses.
Above we where experimenting with layouts using vero-board and real parts or paper cutouts to find arrangements that work, now use paper cutouts to work up a ground plane arrangement that leaves all the pins we need to access at least one pad space and at the time links all grounds with as low an impedance (short distance, wide track) as possible.
Once you worked it out in paper (several times if needed), cut two copies out of the copper-foil using an exacto mini knife, with all the sections removed where we need no shorts.
The way this can look is shown by Naim in this Image:
image Courtesy of Lampizator
The arrangement of the decoupling capacitors however is way suboptimal, avoid copying this, after all, we want high performance here!
Next, attaching your copper foil ground-plane to vero-board.
You need to tin one side of the copper foil, if the vero-bard is not pre-tinned (nowadays they are often gold-flashed) tin all the pads/vias the copper foil is going to cover as well, except those that will later hold IC pins (yes, planning is definitely required).
Paste you copper-foil on top, start by heating your copper-foil with a big soldering iron in corner, so you can make sure it positioned perfectly and if needed slightly shift it to fit. If you get this wrong you will be needing new vero-board and copper-foil, BTW.
Okay, now we solder the whole surface of the copper foil to the vero-board, which will incidentally also tin the surface and stop it oxidising. do not solder where IC Groound pins will be, we solder that later.
Did I mention using brasso to clean the foil super shiny? - probably not, well do it before you cut and use cotton gloves handling the foil, or not, depending how neurotic you are.
Having pasted one side of the foil use a sowing needle (and thimble) to punch the holes where the future IC (ground) Pins will go. Hopefully you did not solder them, otherwise you might as well re-drill them. Repeat for the other side.
Fit the IC's, decoupling cap's etc. and then run the needed wires and foils for signals and supplies.
If you spend some time and effort on this you will have a result that most 4-Layer PCB's cannot match, in terms of optimum current loops and ground impedance.
Of course, you can also integrate your oscillators (whatever takes your fancy) and other parts to implement whatever interface you like and with isolation in the same manner, many of the parts needed for this are still available in DIP format and while this is by far from optimum, you can easily do better with well implemented DIP parts than most get with badly implemented SMD parts.
Or you can buy one of John Browne's DAC's or if you are more a BIY than DIY type and all of this is a bit much, audition some decent commercial implementations and buy the one that combines affordability (to you) with good sonics (to you)...
Ciao T
Hi Thorsten,
Thank you.
Should I'd go for it, I'll invest in real 4 or 6 layers PCB.
I will embark this project only if I'll have a very good SPDIF -> I2S schematic.
John has no DAC to sell at the moment. His latest version is still being developed.
Thank you.
Should I'd go for it, I'll invest in real 4 or 6 layers PCB.
I will embark this project only if I'll have a very good SPDIF -> I2S schematic.
John has no DAC to sell at the moment. His latest version is still being developed.
Chapter and verse please. I have found none from reading the datasheet so would appreciate a heads-up. Perhaps there's something I missed
Chapter and verse please. I have found none from reading the datasheet so would appreciate a heads-up. Perhaps there's something I missed
If we are talking about the same AD RF attenuator, have you looked at the distortion? I don't mean to be an impedement to creative thinking but the last thing we want is to add an attenuator that has more distortion than a typical 12AX7 tube, but hopefully we are talking about two different IC's.
I've done more than look at it, I've measured it (in single-ended output mode). Its of the order of 0.05% at full output, falling to bellow the FFT plot's noise at lower levels. Which pretty well agrees with the datasheet - predominantly 2nd harmonic, 3rd harmonic about 6dB down on 2nd. Now I'm running the part with differential output, I have yet to measure but expect to get 0.03% of relatively pure 3rd harmonic at full output.
I'm not familiar with tubes myself. In any case the THD figure is way less important than the IMD - even for normal audio band duty. Here we have an amp exposed to extreme levels of RF into the 10's of MHz.
Hi,
AD60X or similar I presume? BTW, there are options in AD's lineup with more attenuation range and other interesting features? Look at the equivalent schematic shown for the attenuator in the datasheet.
There is no magic, it is a simple switched ladder and what do you presume they use as switches?
Ciao T
Chapter and verse please. I have found none from reading the datasheet so would appreciate a heads-up. Perhaps there's something I missed
AD60X or similar I presume? BTW, there are options in AD's lineup with more attenuation range and other interesting features? Look at the equivalent schematic shown for the attenuator in the datasheet.
There is no magic, it is a simple switched ladder and what do you presume they use as switches?
Ciao T
Thorsten, thankyou for taking the time to post this useful info. I was going to try one of the the protoboards with a power /ground plane on top and bottom and each hole "isolated" with a gap. But sounds like your technique would be cleaner than a swiss cheese ground plane.
Still the biggest hurddle is finding a means to have the masterclock in the DAC, with the I2S source galvanically isolated.
Would it be nuts to proposed galvanic continuity all the way from the usb ground thru the DAC and provide galvanic isolation on the analog side with good transformers?
If we are careful with keeping the current loops of all our decoupling small maybe this is a decent route for the DIYer?
Or likely still no better than using wm8805 spdif for the galvanic isolation from the computer/transport and giving up on a real master DAC?
Also you haven't talking about the analog section, I posted my thoughts in the big thread. In my head I can't accept that a single common gate mofset is suitable solution for an ultimate DAC. I mean 6 years 400 posts working on the digital side and we are going to dump the output into a single mosfet and expect this is the ultimate DAC? I suggested some brainstorming for step-up transformer I/V + tube as an alternative but he didn't understand the point I was making.
What are your thoughts on the analog side with regard to I/V conversion with attention to minimizing compliance voltage adding distortion?
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I can only suggest that you return to the datasheet and digest it better. Its a ladder for sure, but where do they say its a 'switched ladder' ? Chapter and verse please.
I don't know Abraxilito you have posted some great ideas over the years but I don't know about this one
You have distortion -65db, is this at 2Vrms output? Also IMD is just about directly proportional the THD unfortunately even when its only 2H & 3H, so you will find high IMD as well
I don't know Abraxilito you have posted some great ideas over the years but I don't know about this one
I'm comforted by the motto 'All new truths begin as blasphemies'
No the AD605 has only 5V supply, so it can just about get up to 1VRMS output per side. 2VRMS in balanced, using both halves of the chip.
Also IMD is just about directly proportional the THD unfortunately even when its only 2H & 3H, so you will find high IMD as well
Reference for this claim? I'm all ears. Stuff designed for RF duty tends to sound fairly good to my ears, this is no exception. I'm still getting audible improvements from applying better filtering to the input of this chip which tells me intermod with out-of-band signals is a major sound quality issue, rather than in-band THD. Of course THD might be an issue too, but I'm sure my speakers are considerably worse at distortion than this device.
Isolation - use ISO/ADuM chips available from TI/AD, these are made for it.
Reclock the i2s near the TDA with local clock.
Send the clock thru other ISO/ADuM and some glue logic to the transport, which can take the sync signlal.
That's easey!
Well its simple maths, I read a great illustration on the web and will try to find it. Now of course higher order harmonic distortion creats proportionally worse IMD, but with THD at .05 the IMD is still going to be high (for a DAC) just from the heavy 2H & 3H.
When I read your blog I thought of the the old TDA1543 as a DAC that most now consider to have too much distortion, Its THD at full scale is -75dB, the benefit this DAC has is it can perform when paralleled to give decent output with a simple I/V resistor (i.e. doesn't add distortion with a fairly high impedance on its output.)
So to an outsider looking (not knowing which DAC chip you are using) at your I/V proposal with -65db THD is going to be similar to the the once popular multiple tda1543's + resistor. I would imagine though that your proposal would have lower noise and better resolution and also the TDA1543 distortion harmonics are different so your proposal is interesting. For me personally I am always looking for low THD prior to my amp, since its obviously going to be multiplied (IMD too.)
I agree on the philosophy that stuff designed for RF can be a good match for DAC's because the high bandwidth of the dac output is handled properly, this is where the discrete vs opamp IV battle started on here almost a decade ago
.
Hi,
Let me put it this way. If you use a WM8805 and you implement it well and take a little care at the source you can get well under 200pS Peak-Peak jitter and RMS jitter below what is needed to keep the degradation for 16 Bit digital audio to a minimum. I would not as such argue that further improvements are not audible, but they are nit great.
Equally, Joseph K. measured the M2Tech HiFace AFTER modifying it with clean power supplies (and I think better clocks) at even lower jitter than that, so I refuse to loose sleep about this when using a 16 Bit DAC.
With the Hi-Face no-one stops you placing the clock circuitry directly at the DAC and sending it back to the HiFace. With the WM8805 you need to program it so the high drive clock output outputs MCK and use that to drive your reclocker (needs programming). Sure, it is not going to be the lowest possible jitter, but it's going to be a darn side better than mosbunall SPDIF input out there.
Sure, why not? Cannot do any harm.
I think so.
That is an option that is certainly workable.
Remember, Jitter of the datasheet/eval fixture implemented WM8805 is around 50ps when fed a jitter free signal... So it can provide very low jitter if given good power supplies and a low jitter source to start with.
I did. I said I'd probably use something like the CEN.
Why not? As said, personally I'd go CEN, which is basically the same 2-way.
The CEN using 2SK170BL and 2SJ74BL has around 12 Ohm input impedance which keeps within the stated +/-25mV compliance. Incidentally, I would not put to much weight on the +/-25mV spec, you can have a fair bit more before distortion rises measurably.
For anyone with a pathological fear of coupling cap's they may be replaced with current mirrors, which incidentally create then the correct polarity, another pair of 2SK170BL and 2SJ74BL can then be used as followers to create low output impedance (12 Ohm).
My various Tube Stage option are widely documented, so I do not repost them.
Ciao T
Let me put it this way. If you use a WM8805 and you implement it well and take a little care at the source you can get well under 200pS Peak-Peak jitter and RMS jitter below what is needed to keep the degradation for 16 Bit digital audio to a minimum. I would not as such argue that further improvements are not audible, but they are nit great.
Equally, Joseph K. measured the M2Tech HiFace AFTER modifying it with clean power supplies (and I think better clocks) at even lower jitter than that, so I refuse to loose sleep about this when using a 16 Bit DAC.
With the Hi-Face no-one stops you placing the clock circuitry directly at the DAC and sending it back to the HiFace. With the WM8805 you need to program it so the high drive clock output outputs MCK and use that to drive your reclocker (needs programming). Sure, it is not going to be the lowest possible jitter, but it's going to be a darn side better than mosbunall SPDIF input out there.
Sure, why not? Cannot do any harm.
I think so.
That is an option that is certainly workable.
Remember, Jitter of the datasheet/eval fixture implemented WM8805 is around 50ps when fed a jitter free signal... So it can provide very low jitter if given good power supplies and a low jitter source to start with.
I did. I said I'd probably use something like the CEN.
Why not? As said, personally I'd go CEN, which is basically the same 2-way.
The CEN using 2SK170BL and 2SJ74BL has around 12 Ohm input impedance which keeps within the stated +/-25mV compliance. Incidentally, I would not put to much weight on the +/-25mV spec, you can have a fair bit more before distortion rises measurably.
For anyone with a pathological fear of coupling cap's they may be replaced with current mirrors, which incidentally create then the correct polarity, another pair of 2SK170BL and 2SJ74BL can then be used as followers to create low output impedance (12 Ohm).
My various Tube Stage option are widely documented, so I do not repost them.
Ciao T
I've been searching for an understandable treatment of this for quite a while. So if its really just 'simple math' its surprising nobody's run with it and produced an idiot's guide.
But my measurements show its only high at high level. Just pull up any track on Audacity and see where most of the content is - on the kind of music I listen to, which is classical and acoustic, there's only the occasional peak close to 0dBFS. The real action is almost all happening down below -6dB. So to me its a nonsense to dismiss a part solely on its full level distortion - how that figure changes with level is way more important.
But if most consider it has too much distortion, why do most also use it in a way which makes that -75dB figure even worse? That is by using passive I/V with large changes in the output compliance (several volts in many cases, running on 8V supply). Using a DAC in this way is well known to generate some significant low-order distortion due to less than infinite output impedance. Again it doesn't sound too bad - probably because for real world signals the distortion most of the time is much lower.
Yep - accepted. Except those approaches put the burden on whatever the next stage is - so the results will vary a lot, depending on what its feeding. I'd like my design to be a bit more consistent, hence my approach.
I'm a bit different - I'm looking for low enough THD, not low THD. THD is well known not to correlate with sound quality. So with this design I'm paying attention to IMD with OOB signals and working to minimize that as I have found significant correlation with perceived SQ.
Isolation - use ISO/ADuM chips available from TI/AD, these are made for it.
Reclock the i2s near the TDA with local clock.
Send the clock thru other ISO/ADuM and some glue logic to the transport, which can take the sync signlal.
That's easey!
Thing about thos adum chips, if you read the datasheet I think they are going to do more damage than good. Look at their concern for Rf interference and how much it emits, they run at some 100 mhz? I mean when was the last time you saw warnings about RF emmsion in a datasheet for a compnent you are using in an audio circuit? Plus I'm pretty sure a lot of the 400mhz noise from the computer can jump right thru the adum's. To me using one of them isn't much different than placing a pentium cpu on board next to your tda1541.
Now I have heard your idea proposed to work with optocouplers which I think is probably worth trying. The jitter they add would be eliminated by the alignment at the DAC.
Of course we still have the open issue that with asynch USB, a TDA1541 becomes a 15 bit DAC do to its incompatability with 64bit I2S, so more glue logic on the DAC side.
But I think a project like you propose only using GMR's instead adums and coming up with the 64 to 32 bit conversion would be a great TDA1541 PCB project, possibly leaving the analog stage off for people to work out on their own. Ideally someone with the Xmos or whatever asynch usb chip rights would could offer this as a single PCB.
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Hi,
Doing this (passive I/V conversion with around 2V RMS out and around 8V supply) with the TDA1543 with the reference resistor trimmed for lowest HD can give well below -80dB 2nd Harmonic with all else lower (some chips are outliers though with much higher HD). You can go lower using multiple chip's in parallel but that somehow does not sound as good as a single.
It does not sound bad at all and trying this by now nearly 14 Years ago convinced me that there was something very wrong with the then (and still) dominant way of doing digital audio...
Ciao T
Doing this (passive I/V conversion with around 2V RMS out and around 8V supply) with the TDA1543 with the reference resistor trimmed for lowest HD can give well below -80dB 2nd Harmonic with all else lower (some chips are outliers though with much higher HD). You can go lower using multiple chip's in parallel but that somehow does not sound as good as a single.
It does not sound bad at all and trying this by now nearly 14 Years ago convinced me that there was something very wrong with the then (and still) dominant way of doing digital audio...
Ciao T
I wished I had bookmarked that IMD explaination, it was from a musician/studio perspective and made a lot of sense. Basically when you have two tones the 2H and the 3H add up to give frequencies that aren't harmonically related to either of the first two tones because you have distortion of the distortion, and when playing music with multiple notes this all adds up. Basically THD can be the direct source of IMD, put another way any non-linearities be them harmonically related or not add to the IMD quotient when dealing with more than a single frequency.
Its easy to see when you have a simple tube stage with low noise and only 2H &3H, run the two tone imd test and you will see the non-harmonics pop up (obviously more when their is 4H and especially 5H.)
I agree that THD doesn't correlate well with sound quality but I don't think IMD does either so my questions about your I/V idea are just discussion and curiosity.
What's the theory behind trimming the reference resistor for lowest HD? Just getting the waveform centred between the two end-stops?
To me the advantage of paralleling the chips is to get better low-level distortion. Already I feel -75dB is plenty good enough at full-scale. Haven't yet noticed a single chip sounding better than my paralleled set-ups (which allow more flexibility in choosing the I/V resistor value - the AD605 already contains its own resistor). Perhaps I haven't been listening hard enough....
Yeah, just playing catch-up here some 13 years behind you
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