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Old 11th March 2012, 10:14 PM   #421
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Ok, 10r resistors are everywhere, PSU wires + caps, DECOU caps and DEM cap are there too. Need some 100r for i/v and ground connections to start. Tomorrow i hope to run it
The 1541 doesn't have single direct connection - everything is thru resistors. It should "skew" the PSU voltages when powered on, based on current demand. By the way, would it oscillate in such case? I want to see "bare" unfiltered currents as worst-case scenario.
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Old 11th March 2012, 10:44 PM   #422
Previously: Kuei Yang Wang
 
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Hi,

Quote:
Originally Posted by s3tup View Post
Ok, 10r resistors are everywhere
If you cannot buy or have a 1X100 active probe, please make a suitable preamp and drop resistors to 0.1R...

Ciao T
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Old 12th March 2012, 12:58 AM   #423
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I haven't found any active probes which actually multiply/amplify, not to mention their price.
Preamp? Which suitable bandwidth is doable? FET, OpAmp based?

I can drop the supply to 1R given the scope's 2mV/DV and TDA's specs of 20-40mA.
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Old 12th March 2012, 01:28 AM   #424
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You could try using AD605 as a preamp, it has considerable GBW (we are talking >1GHz) and a minimum gain of 34dB.
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Old 12th March 2012, 06:03 AM   #425
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Hi,

Quote:
Originally Posted by s3tup View Post
I haven't found any active probes which actually multiply/amplify, not to mention their price.
Preamp? Which suitable bandwidth is doable? FET, OpAmp based?
Personally I use a cascoded low capacitance J-Fet with a follower, bandwidth is something like 10MHz, depending on source impedance.

Just look at any wideband radio frequency stuff...

Ciao T
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Old 22nd April 2012, 03:04 AM   #426
ozcal is offline ozcal  Australia
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Quote:
Originally Posted by ThorstenL View Post
Hi,



PS, connect 100uF/6.3V across the cathode to Adj resistor (R5, R7, R9, R13) to get the lowest possible impedance from the TL431, quality is not super critical, so no need to go Os-Con or Black Gate.

And if you replace the CS8412 with a CS8414 on adapter you should get a C0G 0603 SMD Cap (3300pF) and fit it directly at the CS8414 Pins and remove it from the main PCB. In fact I would probably move the whole set of parts on the FILT pin of the CS8412 to SMD and onto the adapter PCB.

C31, C36 and c39 are worth putting large values (small physical size) in place, C9, C11, C13 can use Elna Silmic.

Ciao T
Hi T , with the 100uf/6.3v caps which way round are they connected acroos the resistor? IE does the negative of the cap go to the cathode or to the ADJ?
Thanks,
Gordon
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Old 22nd April 2012, 04:38 AM   #427
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Hi,

Quote:
Originally Posted by ozcal View Post
Hi T , with the 100uf/6.3v caps which way round are they connected acroos the resistor? IE does the negative of the cap go to the cathode or to the ADJ?
Negative to adj of course. Also, watch the 6.3V rating if you happen to have more than 8.5V final DC across the 431. With 15V you need to use 16V/100uF.

Ciao T
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Old 22nd April 2012, 09:07 AM   #428
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Rargh, not yet investigated anything.

But kinda preview of what i have...


And again, i decided to go with CPLD on digital end to get more control on clocking, I2S etc.

What i want to do is feed the TDA in simultaneous mode. I'll halve the clock rates - therefore less disturbances, and ability to go 8x oversampling.

In addition, going CPLD brings possibility to use dufferent DF ICs which aren't compatible with 1541 by default. There are many nice DFs around which were no-no for 1541 due to their high BCLK rates.

I want to implement advanced clocking scheme, which will give ability to
- Slave/Master operation of SPDIF receiver
- OS/NOS operation
- Support of Hi-Rez 88.2, 96, 172.4, 192kHz formats falling back to NOS with DF bypass.

Moreover, dual-differential mode with two TDAs becomes possible as CPLD could split/invert the i2s to L+,L-, R+,R- signals, and pack each channel pair to single I2S line (or even simultaneous way).

That will require 2's compliment to binary offset conversions etc. The VHDL thing is pretty neat and new for me, and i like it. Tiny power, tiny footprint, flexibility and "hardcoded" design. I've already coded i2s inverter with two 32-bit arrays (shiftregs in hardware).


In addition, to futher reduce digital noise on DAC board, the reclocker should work with 3.3v levels - we don't need the 5v swing anyways, and working with 3.3v both reduces voltage swing, and slows down slew rate.
And best of all, the clock driver could be 5v, but with series-paralel termination dividing the signal in half, and bringing down the logic levels to 3.3v CMOS-compatible, with no reflections on either ends of transmission line.

The problem is... I have one quad DFF on the DAC for reclocking, but need to reclock 5 signals (data_L, data_R, BCLK, LRCLK, DEM_CLK). Argh, a bit on the FAIL side. Is there any TinyLogic (or comparable) DFFs which both have slow slew rates and differential outputs? I hate going the octal DFF ICs without differential outputs just to have an possibility to go simultaneous mode...
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Last edited by s3tup; 22nd April 2012 at 09:23 AM.
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Old 23rd April 2012, 08:33 AM   #429
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Hi,

Quote:
Originally Posted by s3tup View Post
What i want to do is feed the TDA in simultaneous mode. I'll halve the clock rates - therefore less disturbances, and ability to go 8x oversampling.
Yes, but the CPLD needed will create problems for most DIYérs.

Quote:
Originally Posted by s3tup View Post
In addition, to futher reduce digital noise on DAC board, the reclocker should work with 3.3v levels - we don't need the 5v swing anyways, and working with 3.3v both reduces voltage swing, and slows down slew rate.
Then you need to re-calculate the I2S attenuators.

Quote:
Originally Posted by s3tup View Post
The problem is... I have one quad DFF on the DAC for reclocking, but need to reclock 5 signals (data_L, data_R, BCLK, LRCLK, DEM_CLK).
So? Use a Hex or octal FF instead.

Ciao T
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Old 23rd April 2012, 09:01 AM   #430
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Quote:
Originally Posted by ThorstenL View Post
Hi,
Yes, but the CPLD needed will create problems for most DIYérs.
I doubt whether DIYers will want to build my DAC , but whenever they do - i can supply programmed CPLDs... I'm going with PLCC package and sockets, so DIYer could switch the programmed ICs or program 'em themselves, given the source is provided as well as compiled core and instructions. Programmer isn't that cheap (Xilinx SW compatible goes for ~$50, cheap alternative goes for ~$15)... CPLD ICs are around $2-$5, which isn't that bad given the possibilities they bring... JTAG connector will be there.

I like the "single board fits all" thing, it seems i'll be able to make it compatible with most DACs around, both single and dual, and with different clocking schemes including ASRCs.


Quote:
Originally Posted by ThorstenL View Post
Then you need to re-calculate the I2S attenuators.
Shure, i'll tweak the attenuators/ slew rate filters in place and give appropriate values, as well as other circuit parts.

Quote:
Originally Posted by ThorstenL View Post
So? Use a Hex or octal FF instead.
I already had a bad time finding quad DFF with differential outputs.
Here are part numbers of "TinyLogic"-kind of devices with appropriate Q andQinv outputs. They need to be futher filtered for 5v-tolerant inputs and 3.3/5v Vcc operation.
NC7SP74*
NC7SV74*
NC7SZ74*
74LVC1G74*
74LVC2G74*
TC7WH74*
SN74LVC2G74*

But, prior to going with them, their layout in 2-sided (actually 1.5-sided) board should be reconsidered, as they require too many traces...
Ehm... I checked it. It seems unroutable in 1.5 layers without ruining CLK trace impedance. Paralel termination is a must in case of multipe inputs.

Going for single-ended DFF just because a feature of simultaneous input?
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