24 channels USB to I2S interface (with Source codes, ASIO/VHDL/Schematic)
Hi Now I'm making my USB-I2S interface.
I made stereo and 8channel USB-I2S project 2007 and 2008,
now expanding to 24bit 24 channels.
(1) Board photo, UM232H module / IDT72V FIFO / DLP-HS-FPGA2 / Clock, Power, Buffer
(3) VHDL source, single, about 800 lines. 1300 FFs.
(4) ASIO Host Driver source, about 600 lines. (ver 0.1! I want to tune)
(you need ASIO SDK and free VisualStudio to build)
FIFO can be changed to Cypress or faster one, if you want synchronous speed.
FPGA module can be changed. maybe GameDuino, Lattice Brevia, etc will work.
Clock, more can be added to switch 44.1/48/88.2/96.
Isolation, you can add IL711 isoLoop.
Power supply, is your free choice.
by looking into source code, you can find only some lines are specific for FTDI. and 90% of codes are for ASIO. the core is to make data format for the device, then write them to the device. about 40 lines.
I only uses very simple VHDL, to understand / to modify. If you can read state-machine, you can read.
Now you have all materials to start your own, don't ask me - please DIY and enjoy:)
Koon, great post, thank you, you have me thinking about an alternative method of implementing multi-channel bit perfect i2S. I have source code for a virtual sound card driver (MSVAD sample) that could be easily hooked up to the UM232H module, and through implementation of a simple serial protocol the hi-speed of the USB serial interface can easily cater for multi-channel. The virtual soundcard driver would be a nicer way to implement it as any application can use it, and not have to rely on tricks like ASIO4ALL inbetween to connect.
Even though the interface will not be standards based (eg. UAC2) that does not really matter. I also have dug deep into the FTDI modules in a previous project and 40Mbytes/sec is ample for hirez multichannel. Having a quick look at your code, I can't see how you are using the FTDI chip in hi-speed mode as you set the output baud at 115200? Or is this your signalling channel back to the PC (I haven't taken a good look at your code yet).
I'm thinking would it be easier to use a microcontroller like the Pic DSP series instead of the FPGA (use the SPI ports as I2S)?
Great work, I was @ Your site...wow
cheers + thanks
Speed: UM232H is EEPROM programmed as 245 style FIFO, by MPROG utility. maybe "115200" has no meaning for FIFO mode, please forget.
IDT FIFO and UM232H both runs in 4 cycles / 60MHz, achieved up to 15MB/sec PC-FTDI-FIFO-FPGA, when tested.
MCU: I think dsPIC can output single I2S only ??
Yes, dsPIC doesn't have the I2S ability although I think you can use either the SPI ports or even bit banging on GPIO pins
I'm not familiar with FPGA, but couldn't you implement the FIFO in the FPGA? ALso it looks like there is a FTDI development card (Maestro) which has both the FTDI hi-speed USB chip and a FPGA on the same card, and it can use an external clock.
ALso, why are you using a separate FIFO? The UM232 has an onboard FIFO as well as 1K buffer. Are you using 512 bytes bulk transfer mode?
implementing FIFO in FPGA is possible, but it makes VHDL more long / confusing, and specific for Xilinx.
current design is very 'generic' and as I wanted, easy to understand. complex problem is broken down to ASIO host / FIFO / FPGA.
everything on the generic prototyping board, so anyone can change power / clocks / isolation.
on chip FIFO is too small. 1KB can contain only 13 samples, this is 68usec for 44.1kHz. No program can put next samples in this cycle.
looks like everyone is doing a USB to I2S converter these days.
you'd better watch that the chinese don't package it up and offer it on ebay for $99 ;)
try to read VHDL. I only use if-then, case-when, and signals.
process() = function(), and signals are global variable.
I was thinking if I use MCU.. and still large VHDL exists.
Trev, $99 is great:) I spent $300 or so.
PCI VHDL is free IP, so someone can try in single FPGA PCI card..
Can you explain a little more about:
1) How resilient this design is for jitter performance
2) How do you manage the FIFO buffer to avoid over/underruns? I assume the PC sends its data full speed but how do you manage the FIFO buffer control? Its not obvious in your code.
3) Do you have a description of the serial protocol you use between the PC driver and the FPGA. How do you differenciate between the serial samples (header, timing etc?)
4) As I understand it, a FPGA needs to be programmed every time it is switched on. Do you send the program over serial? Wouldn't a CPLD be a better choice (sorry I am FPGA/CPLD newbie).
5) For PC/USB isolation, I assume its best to isolate the 8 data lines out of the FTDI module so that any added jitter is buffered by the FIFO
This is a very interesting approach to USB audio!
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