24 channels USB to I2S interface (with Source codes, ASIO/VHDL/Schematic) - Page 3 - diyAudio
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Old 17th November 2011, 04:27 AM   #21
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Hi dean, making PCB? it sounds great, but please watch your step.
FPGA programming / debug cycle is very long, if you are not completely understanding what you wrote / how it runs, it will be hard way to go.
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Old 17th November 2011, 04:36 AM   #22
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In case you need,
Attached very simple FTDI - FIFO - FPGA playback test program.
only requires FTDI D2XX header and library. (without ASIO)
This program accepts one argument as WAV file name.
44.1/16 or 24.
Then reads all data into memory, and start playing.
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File Type: txt FTDIonlyTest.cpp.txt (5.9 KB, 58 views)
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Old 17th November 2011, 11:30 AM   #23
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has anyone read this ?? Interesting article about USB audio from Audio Research.

http://www.audioresearch.com/downloa...hite_paper.pdf
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Old 17th November 2011, 12:04 PM   #24
deandob is offline deandob  Australia
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Thank you Koon. I will work it with the sim first. I have a fair bit of MCU experience but I appeciate your advice, breadboard first!

Trevor, good summary of USB audio options. Note this option is not USB Audio compliant and uses a different model (FIFO buffer) not described in the paper (although quality should be equivalent to "best"). Latency may be a little more with this solution due to the time taken to fill the buffer up to the limit where the FPGA starts transfering the data, should only be in the low msec as the USB transfer rate is very fast (faster than the output sample rate).
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Old 17th November 2011, 10:02 PM   #25
deandob is offline deandob  Australia
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Looking into FPGA makes/series at the moment. Does anyone have any data on which FPGA make/series has low jitter output, or what techniques can be used to lower jitter on the output of the FPGA? I'm not talking about the clocks, but the inherit jitter in the FPGA itself through internal gate switching (also jitter may be irregular depending on the logic path taken for the signal).
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Old 18th November 2011, 04:48 AM   #26
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now I'm listening through foobar - Reaper - my ASIO driver.
But foobar direct has some trouble, (1) does not show time info, (2) no graphical FFT meter, (3) when stopping, debug assertion (no source code for foo_asio_out.dll)
maybe.. ASIOTimeStamp function? I need to look into foobar plugin structure.
Attached Files
File Type: txt koonasio01_20111117.cpp.txt (17.7 KB, 31 views)
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Old 23rd November 2011, 11:12 AM   #27
deandob is offline deandob  Australia
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Koon, check with the foobar forum at hydrogenaudio (developer forum) for your ASIO question.

I have a couple more questions as I have considering a design similar to yours (and a good learning exercise for FPGA). Why did you use an expensive FPGA board? I have loaded up your VHDL code into Xilinx Navigator and got it to compile easily with a small CPLD, which is a much simpler and cheaper alternative. You don't need too many logic blocks for this function (although I'm considering using SDRAM which needs a lot more code to manage the SDRAM as a FIFO).

Also, why did you mention to isolate after the FPGA? A better option would be to isolate between the FTDI board and the FPGA, then any extra jitter added by the isolator will be removed by the FIFO, and the FPGA can share the digital ground with the other digital logic.

To optimise your design for even lower jitter, use a low jitter flipflop (like the potato ones) as a reclocker for the I2S outputs.
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Old 23rd November 2011, 02:27 PM   #28
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Hi dean,
Please don't think my design is 'reference'.. just a doodle
FPGA module: I have some FPGA module, in this case 50 pin is good.
of course you can replace to any other CPLD, FPGA if VHDL fits in.
SDRAM: yes you can use SRAM/SDRAM or FPGA internal block RAM. why I use external FIFO is, that is not a point of the VHDL. (sample code should be simplified)
This DLP design board can implement everything(USB interface, SDRAM, VHDL) in this module, but that is not a good sample.

Isolation point, power, clock, buffer of FF: if isolation between PC and external, you can place Isolation around UM232H.
for Isolation between your DAC and other digital, then should be after FPGA.
FPGA can be the source of clock (power supply) jitter, because it uses different clock.

FlipFlop/reclock: also, Master Clock on this board or Master Clock on the DAC | reclock on this board or reclock just before DAC | is selectable.
I use TI digital amplifier so I only need buffer / clock on this board.
If you use splendid DAC, you will pull Master clock from DAC, and isolation / reclock will be placed just before DAC.
you can modify as you like. please enjoy.
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Old 26th November 2011, 01:35 AM   #29
deandob is offline deandob  Australia
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Koon, it seems according to your schematic that you are using a 8K FIFO. Did you try this design with just the 1K FTDI internal FIFO? If you keep the channels to 8 and sample rate to 96Khz then you should be able to get about 40 frames into the 1K FIFO buffer which is about 0.5msec worth of buffer, for High Speed USB should be enough (buffer of 2 x 512 bulk transfer USB packets). However with a small FIFO the design will be open to dropouts if the PC can't keep the packet rate up (bulk mode does not guarantee timing).
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Old 26th November 2011, 02:39 AM   #30
deandob is offline deandob  Australia
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Further research has answered this question.

Even on a lightly loaded USB bus, Windows may cause delays in USB bulk transfer requests, so there is a high chance of buffer underruns and gaps in audio output on a Windows system using this approach. Basically the FIFO buffer between the FTDI module and the FPGA/CPLD should be as large as possible to minimize overruns. I've been trying to decide what hardware to use for my prototype (CPLD with FIFO chip, or FPGA with SDRAM), and for some reason even medium capacity FIFO chips are very expensive, so if a large buffer is needed, a FPGA with a cheap SDRAM chip is the way to go. Note with a FPGA and SDRAM approach typically you need to implement both the SDRAM controller (dual port for async) as well as the FIFO logic. Luckly there are reusable code blocks for these functions.
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