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Old 14th November 2011, 02:10 AM   #31
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I thought that being copied was an honor in China? That proves that you do a good job?
Ah, honor doesn't pay the bills? They finally figured that one out...

PS: I like some of the chinese (taiwan) DAC's on eBay. Tempted to buy one just to see how they are really build. Some of them I bet are posting on this site, I can spot them from the NOS virus that pops in some of their products

Last edited by SoNic_real_one; 14th November 2011 at 02:15 AM.
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Old 14th November 2011, 02:16 AM   #32
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Quote:
Originally Posted by SoNic_real_one View Post
I thought that being copied was an honor in China? That proves that you do a good job?
Indeed it is, its a way of 'giving face' in the traditional culture. But I'm guessing that this guy's been infected by Western Capitalist mores, he's only paying attention to potential lost revenue.
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Old 14th November 2011, 03:43 AM   #33
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Hi,

Quote:
Originally Posted by SoNic_real_one View Post
I did not say that it does work well. You just cut that part of my reply.
My point is that when you get it to work the WM880X does work well, so they cannot use this particular method you suggest...

Quote:
Originally Posted by SoNic_real_one View Post
I really don't care if 8805 it is "working", I wasn't at all my point.
Sorry for mistaking that. I was under the impression that you felt that WM were lying about how the chip worked AND how it performed.

Quote:
Originally Posted by SoNic_real_one View Post
I care that they deceive purposely about the function of that crystal (on the marketing part of their datasheet)
They lie? You mean like Tony Bliar who said Iraq could deploy WMD's in 15 Minutes when in fact Iraq had non that where in any state to be deployed?

Let's see what they say:

Quote:
Originally Posted by Wolfson Micro WM8805 Datasheet
A crystal derived, or externally provided high quality master clock is used to allow low jitter recovery of S/PDIF supplied master clocks.
I would say that "crystal derived" is a fair description of using a Fractional N DPLL with crystal reference to generate the master clock.

Quote:
Originally Posted by SoNic_real_one View Post
and probably about the FIFO buffering.
Well, I have not been able to analyse the WM8805 on a silicone level, so I cannot 100% confirm they use a FIFO and the FIFO Fill Level to control the frequency programmed into the Fractional N DPLL clock generator.

However, it seems an eminently workable principle and the WM880X certainly works using this programmable clock (otherwise there would not be the 176.4/192KHz locking issue).

Quote:
Originally Posted by SoNic_real_one View Post
And that false information gets spread on forums...
Yes, it does, doesn't it. The only question here is who actually is spreading lies, innit?

Quote:
Originally Posted by SoNic_real_one View Post
Then people ask legitimate questions like the one that started that thread "why is not sounding better"?
Well, "Why does it not sound better?" is a valid question.

My point is that, if a DAC build with CMOS IC's that are operating at clock rates in 10's of MHz range and only uses electrolytic decoupling capacitors placed an inch or more from the IC's they are decoupling in violation of the manufacturers application recommendations for these chips, then the answer to this question may not be to blame the WM8805 based receiver first. In fact, the design flaws in this DAC are so numerous, I find it hard to start to even enumerate them.

And even if the DAC to which said debated receiver module was fitted did not suffer such gross design flaws and the problem was the actual receiver plugin, it would unsafe to automatically assume the WM chip alone was to blame and to ignore the implementation completely.

Ciao T
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Old 14th November 2011, 12:06 PM   #34
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Thanks for the ground tips and closer decouplig. I found an interresting paper on grounding in mixed signals systems (attached), and seems the chineese followed it pretty well, except getting the decoupling caps closer to the ic's . On the other hand, since each noisy ic has his own power supply, this might be less of an issue, since they don't have much else to inject noise into.

Grounding doc PDF 192K

Last edited by mfrimu; 14th November 2011 at 12:10 PM.
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Old 14th November 2011, 12:16 PM   #35
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Stormsonic,

Quote:
Agree with ThorstenL.
CS8414 is not the weakest link in this DAC. Even input buffer alone is contributing much more jitter than receiver chip.
Are you saying those NAND gates introduce jitter? I'se seen some products like Monachy Audio DIP (highly reviewed) that use a similar technique to raise spdif levels...

Thanks
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Old 14th November 2011, 12:16 PM   #36
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Hi,

Quote:
Originally Posted by mfrimu View Post
Thanks for the ground tips and closer decouplig. I found an interresting paper on grounding in mixed signals systems (attached), and seems the chineese followed it pretty well, except getting the decoupling caps closer to the ic's.
Sorry, but the circuit has no decoupling cap's at teh frequencies at which it works. Simply stick a 'scope on the supply lines and you will see...

Ciao T
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Old 14th November 2011, 12:23 PM   #37
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Time for a bunch of good 0805 100 nF caps and some time to solder those close to the supply pins.

BTW I would replace the output cap for a film type. Edit: I see you use BG N series, no need to replace those !
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Last edited by jean-paul; 14th November 2011 at 12:47 PM.
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Old 14th November 2011, 12:51 PM   #38
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Hi

Quote:
Originally Posted by mfrimu View Post
Are you saying those NAND gates introduce jitter?
These are not NAND gates, they are inverters. They are operated as analogue amplifiers in part with insufficient decoupling. The impedances in the input circuit are wrong and hence the input impedance at SPDIF frequencies (where it matters) will be much lower than 75 Ohm.

When using the Cirrus Logic chips the raised level is a good thing in principle, though the actual implementation in the Lite DAC is criminally incompetent, so it is likely to harm more than to help even with a Cirrus Logic receiver which is actually designed for 5V Peak-Peak AES/EBU levels...

HOWEVER, when using a WM8805 which has a different input circuit the result of this circuit is entierly negative. The input expects 0.5V Peak-Peak and yet it is driven with 5V Peak-Peak which actually exceeds the WM8805's rail voltage and hence will make the input protection diodes on the WM8805 conduct and saturate with interesting and wide reaching consequences.

Look, if you want to convince yourself that the DAC's design is actually good regardless of the facts and that even though the design goes against most things common sense, basic electronic knowledge and the Chip Manufacturers data sheets and application notes dictate, be my guest. In this case it may best not to ask questions to which you really do not want to know the answers.

Ciao T
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Old 14th November 2011, 10:39 PM   #39
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Basic decoupling rules are not followed, that's what I said some posts ago:
Quote:
Originally Posted by SoNic_real_one View Post
And I like to see more decoupling capacitors close to DAC and OpAmp (the ones close on rectifyers don't count) - are they on the back? You need one between each rail and ground. Same on digital side - decoupling is too far "out" from chips.
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Old 15th November 2011, 09:48 AM   #40
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After having checked the schematic of the DAC to understand the comment of Thorsten I see he is absolutely right. Is removing the 74HC04 an option (for the SPDIF side at least) ? So connecting the WM8805 directly to the input RCA. I don't have much time to check further right now.

- Remove the 74HC04 from the input circuit
- RCA input straight to the pad the 74HC04 pin 8 was connected to. Before the 10 nF cap !
- Remove resistors 150 Ohm, 2 x 220kOHm, 1 x 47kOHm and 2 x 10 nF caps connected to the 74HC04
- check if the adapter PCB also has 10 nF cap at the WM8805 inputs, that would mean 2 x 10 nf in series...

Thorsten can you please check if this is right ?
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Last edited by jean-paul; 15th November 2011 at 09:59 AM.
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