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Old 20th April 2012, 08:47 AM   #161
zinsula is offline zinsula  Switzerland
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Hi KlipschKid

Regarding the allowed frequencies, i believe there is a misunderstanding.

Page 22 Datasheet WM8805:
Quote:
Crystal frequencies between 10 and
14.4MHz or 16.28 and 27MHz can be used in software mode.
Table 23 on page 25 shows only some examples. I think it is no problem to use say 22.5792 or 24.576 MHz oscillators.
The only problem is that you have to figure out all the PLL settings....
Table 23 in the datasheet may be misleading, as these are only examples for PLL settings.

Regarding better performance:
The OSC frequency has to be divided for locking to the input stream and also for providing MCLK and CLKOUT.
As MCLK and CLKOUT will be integer numbers of fs, at least one family of fs would not require division by fractional numbers when using an appropriate OSC frequency.

Me too, i cannot find the reference in the datasheet which i had in mind. Maybe it was another document, which stated that synchronous OSC frequencies would be superior. Or maybe it was Thorsten who said this, as he implemented this chip for a commercial project.
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Old 20th April 2012, 09:23 AM   #162
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Hi,

Thanks for your help. You are quite right. I dunno where I got the idea 24.576 wasn't possible. Thank you very much for pointing that out.

In the test conditions on page 8 they state fs = 48Khz and mclk = 256fs so they are using 12.288Mhz as mclk, and they have generated this from f1 = 12Mhz, and f2 as 98.304Mhz ?

So R is 8.192 for the above and this allows us to calculate PLL_N and PLL_K. They say PLL_N should be 8 for best operation.

It seems we can choose 24.576 and set the prescale to 1 to get f1 as 12.288Mhz ? With r as 8.192 we would get f2 as just over 100MHz - beyond their specified limit. So R would need to be 8.138 max.

Can we still use PLL_N as 8 with the above ?

Last edited by KlipschKid; 20th April 2012 at 09:52 AM.
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Old 20th April 2012, 10:11 AM   #163
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Is this possible for a 24.576Mhz xo ?

If we decide R = 8.12
f1 = 12.288 f2 = 99.77856 (within limit)
PLL_N is 8 (optimum), then PLL_K = 2^22 (8.12-8) = 503316 = 7AE14 (hex)

In this case R would actually be 8.1199998856 and f2 =99.7785586937

Have I misunderstood how this works ? Table 27 seems to indicate I might have got this wrong...

Last edited by KlipschKid; 20th April 2012 at 10:41 AM.
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Old 20th April 2012, 11:10 AM   #164
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How about this for 22.5792Mhz xo ?

R = 98.304 / 11.2896 (prescale =1 so 22.5792 becomes 11.2896 for f1) = 8.7074829932
PLL_N = 8
PLL_K = 4194304 x 0.7075 = 2D4766 (hex)
FREQ_MODE 01 , allows 512fs, 256fs, 128fs for 48Khz, 96Khz and 192Khz from 24.576Mhz

This would let us use the CCHD-957.

I'm pretty sure this will work, so pls ignore the other ideas above. So shall we go for a 22.5792Mhz clock ? It'll mean a problem with RS / Farnell but will enable the use of the best of very low phase noise xo's.

Last edited by KlipschKid; 20th April 2012 at 11:22 AM.
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Old 20th April 2012, 12:40 PM   #165
zinsula is offline zinsula  Switzerland
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Hi, yes i think that is OK. Important thing is: PLL user mode or S/PDIF receive mode? I think, in this project it must be receive mode (see page 22), isn't it?

In that case, f2=94.3104MHz would be OK for Mode 1 (192kHz fs) according to datasheet Page 27 below and 28.
For Modes 2/3/4 (32 to 96kHz fs) and Mode 1 (176.4MHz) i think f2=94.3104 MHz is required.

In table 23, none of these f2 frequencies are shown, seems as it is the example for user mode only.
What a mess configuring that part, and especially the 176.4/192 kHz detection in Mode 1.
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Old 20th April 2012, 12:59 PM   #166
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Hi,

Thanks for the reply and your help.

I'm leaving the 176.4 and 192 modes to Abraxalito ! Way beyond me to get them working.

However, for f2 of 94.3104 and 98.304, they will both have R > 8 if the xo is 22.5792 (8.35374 and 8.7075 respectively) so that is looking like the best xo freq to choose to get the PLL_N at 8 as recommended.

11.2896Mhz is also a candidate but that rules out the cchd-957.

I just got a reply from Sylvie at Mercury. She's going to get back to me next week about a 3.3v 22.5792Mhz xo and the phase noise, prices, etc. She says the best is 25ppm but gotta wait and see about the ps.

Thanks again for your help !

Last edited by KlipschKid; 20th April 2012 at 01:01 PM.
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Old 20th April 2012, 01:14 PM   #167
zinsula is offline zinsula  Switzerland
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You're welcome!

Mouser has them (CCHD957) here
I'd have to buy 5 pcs (or the equivalent in value), then they would not charge for shipping (at least to Switzerland).
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Old 20th April 2012, 01:32 PM   #168
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Hopefully, with everyone's help, we can get a really good receiver. It seems people want one... so thanks again. If you see any more mistakes, please let me know... :-)

I already bought two CCHD 24.576 and one 22.5792 for other projects. They are excellent ! Even with nothing more than an adp150 reg.

I haven't tried to create a lower noise supply for them yet - to see if I can get better performance. Have you tried ?

I was thinking about using an LM723 (2.5uV noise) with a BUP40 pass transistor, to create a 7.25 supply, and then drop that down to 4V using a potential divider; (18K, 22K). The 4v can be fed into the base of a bc550, with a 100uF cap to ground, to create a filtered 3.3V with nV noise, if the layout etc is good enough. One day...

Thanks again.
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Old 21st April 2012, 01:31 PM   #169
zinsula is offline zinsula  Switzerland
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Quote:
Originally Posted by KlipschKid View Post
[...]
I haven't tried to create a lower noise supply for them yet - to see if I can get better performance. Have you tried ?[...]
Hello KlipschKid

No i did not buy one yet.

I think i will breadboard something like this. It is similar to what Demian Martin proposed, but as a shunt with pretty high PSSR because of the cascoded depletion MOS-Fet CCS. TL431 is only there to provide stable DC level.

Of course it could be done even simpler, using LED's as reference. Voltage might not be regulated precisely in that case.
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File Type: gif Shunt Reg CFP+TL431.gif (113.1 KB, 161 views)
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Old 23rd April 2012, 11:28 AM   #170
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Hi,

The mosfets are interesting but the tl431 is a little noisy - 40uV - iirc ? Has the circuit been tested ?

I just received the phase noise plots for the XO91 22.5792. Looks good considering it is an inexpensive xo at RS - US$3. I have used it many times and been impressed so it's good to see the plot to confirm this. I am thinking about ordering some direct from Mercury. Is anyone interested in any ? Or should I just order a few for myself ?

10hz -80dB, 100Hz -108dB, 1Khz -128dB etc with a noise floor of -156dB.
XO91 US$3
Click the image to open in full size.
CCHD-957 US$30 ~15 to 20dB better
Click the image to open in full size.
Tent Labs US$40 similar to XO91 but with a lower noise floor
Click the image to open in full size.

Last edited by KlipschKid; 23rd April 2012 at 11:49 AM.
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