I think to start this new thread based on my own recent experience with this ultimate DAC.
I intended in the last time to change the ESS9018 clock oscillator, but I had not at that moment a right one. So I used an 106 Mhz for that max clock frequency specified in datasheet (100 Mhz).
It was accepted very well by ESS9018...
So, afterwords I`ve tried more. I bought one of 125Mhz and one 150Mhz. It was OK with 125Mhz, but didn`t work with 150 Mhz. So, my conclusion was that the limit have to be in this range (125 - 150 Mhz).
Recently I`ve tried with an 133,3 Mhz. It worked!
I have to say that the result of those experiments have been appreciate only perceptual, without very close measurements or any deeper analyses of what is possible to happen inside the chip at this high clock frequency. I had not that time to get closer/deeper in to this. I used both FLAC files and SACD/DSD. Even on ordinary CDs (44,1 khz sampling), the sound is fantastic The resulting sound after this upgrade is just exceptional in details. I never heard a such deeper and sophisticated bass, and the sound stage is amazing, comparing with an 100Mhz clock.
I can not say that ESS9018 it sounds not well with an 100Mhz clock. It could be stupid to state like this. But is a perceptual positive result after changing to a higher clock frequency. The details increasing in the sound is easy to notice.
By the way, my experiment object/DAC is not an very impressive one as design... I had not yet a Buffalo 3 PCB design at the experiment moment... But anyway this one it`s work very well after the modifications one can see in the picture. I think to take a look more seriously on this subject based on a Buffalo mounted ESS9018.
The point is now to share this experience, and invite you to come with your comments, impressions and even a closer look in to this field.
I intended in the last time to change the ESS9018 clock oscillator, but I had not at that moment a right one. So I used an 106 Mhz for that max clock frequency specified in datasheet (100 Mhz).
It was accepted very well by ESS9018...
So, afterwords I`ve tried more. I bought one of 125Mhz and one 150Mhz. It was OK with 125Mhz, but didn`t work with 150 Mhz. So, my conclusion was that the limit have to be in this range (125 - 150 Mhz).
Recently I`ve tried with an 133,3 Mhz. It worked!
I have to say that the result of those experiments have been appreciate only perceptual, without very close measurements or any deeper analyses of what is possible to happen inside the chip at this high clock frequency. I had not that time to get closer/deeper in to this. I used both FLAC files and SACD/DSD. Even on ordinary CDs (44,1 khz sampling), the sound is fantastic The resulting sound after this upgrade is just exceptional in details. I never heard a such deeper and sophisticated bass, and the sound stage is amazing, comparing with an 100Mhz clock.
I can not say that ESS9018 it sounds not well with an 100Mhz clock. It could be stupid to state like this. But is a perceptual positive result after changing to a higher clock frequency. The details increasing in the sound is easy to notice.
By the way, my experiment object/DAC is not an very impressive one as design... I had not yet a Buffalo 3 PCB design at the experiment moment... But anyway this one it`s work very well after the modifications one can see in the picture. I think to take a look more seriously on this subject based on a Buffalo mounted ESS9018.
The point is now to share this experience, and invite you to come with your comments, impressions and even a closer look in to this field.
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We consulted quite a lot with ESS on the subject.
The ES9018 actually begins to lose dynamic range (very measurable) as the clock speeds go past the rise and fall times specified in the datasheet. I was not the first to say this, Dustin Forman the chip designer was. While consulting with him we found that the DAC begins to measure worse after 100Mhz and that the best range is between 40-100Mhz and ~80Mhz is actually the sweetest spot when we measured our DAC by a very slim margin. 100Mhz still sounds and measures quite well but is more forgiving when the DPLL needs to lock onto sample rates > 352khz.
I have tried all sorts of clock frequencies using excellent clocks and personally found anything > 100Mhz less desirable than either 80Mhz or 100Mhz.
Still this poster is not using a Buffalo DAC so I cannot really say much about his experiments, except good luck, and have fun.
Cheers!
Russ
I understand well what about datasheet reveal in this case. It still only a question here: why one can perceptual notice an improvement using these higher clock frequencies?
I`m still waiting for somebody else trying the same on different DAC platforms and come with own impressions... That is actually the reason of this thread.
Very simply the mostly likely reason is because one *wants to* hear the difference, There is nothing wrong with that.
Very simply the mostly likely reason is because one *wants to* hear the difference, There is nothing wrong with that.
I think is not that simple as you want to be... But anyway, everybody with his placebo...
I will stop here to answer to you, because the meaning with this thread is something else...
Coris...
As an aside, but on the same topic, have you tried synchronous clocking? This is going to be my next experiment with the Buffalo II. I have an async USB interface which can provide the masterclock. My plan is to upgrade the oscillators on the USB interface to Crystek CCHD-957s when they become available, and at that point, try synchronous clocking the ESS 9018 from the MC feed over I2S. I am just curious to see what the DAC will sound like without the ASRC, and "virtually" disabling the DPLL.
In my past experience, I have preferred other DACs (TI 1798, Wolfson 8741) without any ASRC, provided that the data feed is low jitter to start with.
As an aside, but on the same topic, have you tried synchronous clocking? This is going to be my next experiment with the Buffalo II. I have an async USB interface which can provide the masterclock. My plan is to upgrade the oscillators on the USB interface to Crystek CCHD-957s when they become available, and at that point, try synchronous clocking the ESS 9018 from the MC feed over I2S. I am just curious to see what the DAC will sound like without the ASRC, and "virtually" disabling the DPLL.
In my past experience, I have preferred other DACs (TI 1798, Wolfson 8741) without any ASRC, provided that the data feed is low jitter to start with.
I certainly have. It works quite well and sounds exceptional, but you have to be extremely careful how you get the master clock from here to there.
I have a really cool method of doing that which I will share soon.
It doesn't just virtually shut down the DPLL, it very actually stops doing anything.
Thanks Russ
I look forward to hearing about your clock distribution method. Very cool that you are working with synchronous clocking. From what I have heard from engineers I respect on clock distribution, it appears it is very hard to keep low phase noise when transmitting a clock signal...
Yeah, on the DPLL, that is why I put "virtually" in quotes-my understanding is that the DPLL would still be active but would not be actually doing anything as the clocks are now synchronous, and woudl not need to be synched.
I look forward to hearing about your clock distribution method. Very cool that you are working with synchronous clocking. From what I have heard from engineers I respect on clock distribution, it appears it is very hard to keep low phase noise when transmitting a clock signal...
Yeah, on the DPLL, that is why I put "virtually" in quotes-my understanding is that the DPLL would still be active but would not be actually doing anything as the clocks are now synchronous, and woudl not need to be synched.
Hi Barrows
For answer your question: no. Not yet... It is a field of experiments this too, but in the same time I agree with the idea that is not quite easy task a synchronous clock distribution with low jitter and phase noise. At these high clock frequencies it is a big challenge to keep it clean enough for all the stages involved... But anyway, without trying, no steps forward.
Dear Coris and barrows,
I assume Coris have removed the original on-board Crystek Oscillator from his BIII DAC board. I'd like to recommend both of you try a synchronous Master Clocking scheme rather than Coris's asynchronous over-clocking approach if you have a good I2S sources.
In my case, I used to adopt 96 or 100 MHz oscillators so that I could play 352.8 kHz/24 bit PCM (DXD) sound sources on an oversampling mode before. After experiencing a superior result of synchronous master clocking and NOS approach for DXD play, now I prefer such lower master clock frequencies as 22.5792 MHz and 24.576 MHz. Even for DXD, the low frequency master clock is effective on NOS mode.
Bunpei
Hi Bunpei
Your approach is interesting. I think I will give it a try (I don`t know when, because is so much to do it...).
For be better understood, I will explain here a little more:
Initially, before get my Buffalo I`ve decided that I will use an oven controlled oscillator (100Mhz) and remove it that original Crystek which come with Buffalo 3. So I bought a such much more precise oscillator for this purpose. In meanwhile I started those experiments with a higher clock frequencies, based first on that fact that I couldn't find at the moment another 100Mhz oscillator to upgrade my Oppo BDP95. So I used that ESS9018 platform in my experiments, waiting for the ordered Buffalo 3. When I got it, I just removed the oscillator at once following the above described idea.
Anyway I will give it a try to Baffalo with the oven controlled clock (100Mhz), and I will try some other solution too. It is more convenient to use Buffalo kit for this purposes, than use a quite bad designed and very big (40/16cm) PCB (Oppo), where is difficult to measure something... Buffalo DAC still be my first priority, but the BDP95 have to function well too... At last this player it has a very good transport, accessible DSD, SATA interface, good picture (after upgrade...), and so on... Only problem with this player is that the dedicated audio stage and it`s power supply looks like have been designed by some first years students...
Using higher (over-clocking) frequencies to clock ESS9018, come in conflict with the chip producer stated parameters. It is risky from chip functional point of view, and not enough analysed at this moment. So, I will not state that this is the best and recommended way to use this ESS9018 DAC. But in the same time it works. The perceptual improvement is a fact, and not a placebo as TPA try to suggest. By the way, I can say the same that for TPA stuff their placebo is well based on right using of the DAC datasheet, orthodox measurements, and so on... Not to forget the commercial/business interests involved in this "placebo" too...
And more something else: there is a fact that ESS9018 accept very high clock frequencies. I just think that is not only by chance that ESS9018 was made in this way. Around this chip was before enough secrecy in revealing it`s functional details. I`m personally quite sceptic that the designer him self have came out with all about this chip, even though much infos was delivered to the TPA. ESS intend to came out with few as possible informations about the product, but in the same time they have to sell it too. So, they only used TPA and this forum as a marketing and advertise platform for their new (at that time) DAC chip. This is not a critic directed against somebody, but just an observation which leaded at last to my conclusion that not all the infos about this chip are out there yet... But anyway...
I`ve tried in my experiments on this BDP95 platform first with an 106 Mhz standard oscillator (50ppm), then the Buffalos 100 Mhz Crystek, then 125Mhz, 133,3 Mhz. I have to say that I`ve registered an perceptual improvement from 106 Mhz to 100 Mhz Crystek. In Crystek favour. Then an improvement from 100 Mhz Crystek to 125 and 133,3 Mhz (those lasts also standard oscillators 20/50ppm). The improvement is quite evident in detailed sound stage, dynamics, and lower end of the audio spectre (bass). For example, in using 133,3 Mhz, an symphony orchestra (CD 44,1 sample recording) just punch in in the lower end of the spectre as it does in real concert environment... One just feel the sound pressure as it does in real... Actually, the real meaning for I`ve came out here with this experiments is to try find a reasonable explanation to those facts...
I still do think that a higher clock frequency lead to more resolution in the resulting analogue signal/finally sound, but as Bunpei state, it could be very possible that opposite works too. So, it still only to give it try, and not only reject everything else because is not in conformity with the producer datasheet...
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Thanks...
Russ and Bunpei. I am going to try synchronous clocking, but it may be a little while before I am ready to do so. I want to make sure I have really great clocks on my sourece first, otherwise this will not be a fair evaluation.
It is nice to see that the B-III board is already designed to easily accept an external masterclock feed as well.
Russ and Bunpei. I am going to try synchronous clocking, but it may be a little while before I am ready to do so. I want to make sure I have really great clocks on my sourece first, otherwise this will not be a fair evaluation.
It is nice to see that the B-III board is already designed to easily accept an external masterclock feed as well.
@ barrows, not as easily as the ackodac, but still yes easier than before. there is already a master syncronous clock module for the ackodac as of a couple of weeks ago. connects by 6ghz micro bnc
sorry Coris, i have to wonder at this terminology you have invented 'perceptual facts' its a contradiction in terms, you cannot have a factual perception, perception is by definition subjective
sorry Coris, i have to wonder at this terminology you have invented 'perceptual facts' its a contradiction in terms, you cannot have a factual perception, perception is by definition subjective
Sorry, but I have to say that English is not my every day language. So it is very possible that sometimes what I want to say/write, not all the time can be very accurate as I intend to say/write.
Anyway my used "terminology" in previous post is not exactly an (my) invention... If it is, then maybe I have to think to patent it...
If you touch something hot, you notice that is hot. It is a very real fact about that thing is hot. Your (human) perception about that thing is hot is (by definition...) a perceptual fact... Appreciating the temperature of that hot thing with the finger it could be very well (perceptual) subjective. The temperature appreciated with your finger is not a fact!. That because it was invented the thermometer... Perceptual facts are facts at last... As you see that outside is day light and is not dark night, is a perceptual fact too... If you see a picture, it is a perceptual fact that that picture exist. If you like what you see in the picture, or not is something else and it is very sure that this is your subjective perception and not a fact...
I think that you (almost) have to (wander to) agree at last with this facts... Your choice anyway...
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Thank you very much for your long explanation.
However, I could not catch which input formats do you always target nor what sampling frequencies, neither.
I think a reasonable clocking approach may depend on those prerequisites.
If you can't ignore S/PDIF input, you can't adopt the low frequency "synchronous master clocking" approach that I told.
If you think the use of over-sampling filter at the play of high sampling frequency sources is essential, your approach is one possible solution.
I'd like to propose one method to prove the effectiveness of your approach. Why don't you read DPLL counter values from ES9018 register at your best clock setting and compare them to those obtained in usual 80 or 100 MHz master clock configuration?
If the counter value shows relatively less fluctuations, the the result might mean your approach is effective enough.
By the way, under the synchronous master clocking, my partner, Chiaki showed that "No bandwidth" for DPLL bandwidth parameter was possible even for the play of 384 kHz/32 bit PCM sources with OSF=ON condition.
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Hi
Thanks for the replay. The input formats are the usual ones at this time. PCM and DSD. I use files in FLAC and PCM/DSD from CDs (44/16 and SACD). This is happen on my Oppo player BDP95. I just start now to put together the Buffalo 3 I`ve got it in the last time...
My experiments are made on the BDP95 platform. The samplings frequencies are 192/24-32 bit...
Thanks for your suggestion about the method to control the effectiveness of over-clocking. It is a very good idea. I will do it for sure. BTW, I think are many ways to read the DPLL counter values from ES9018 register. What is in your opinion a simplest/effective/fastest one?
I have to say that now my ES9018 have an 125Mhz clock. And is working very well (perceptual point of view). With 133.3 Mhz I had some noises in the silence moments of the recordings. I`m waiting for a 128Mhz clock for test with it. I have in mind to test with lower clock frequencies (your approach).
Now I have a question for you and others: have somebody tried to bypass/decoupling ES9018 with 1000µF (ceramic/tantalum) on the AVCC pins (L/R)?
I will not say how it sounds... Maybe somebody else will get curious to try it, and will come here with comments about this experience...
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