ESS9018 - try new, try more...

We consulted quite a lot with ESS on the subject.

I have tried all sorts of clock frequencies using excellent clocks and personally found anything > 100Mhz less desirable than either 80Mhz or 100Mhz.

I found that either synchronous clocking or clock frequencies that match the played samplerate are a huge improvement compared to 80 / 100MHz clocks that are not working optimal with any samplerate.
Clocks above 100MHz that match the played samplerate are not possible as they would need to be in the 180 - 200MHz area.

I now uses four alternative clocks setups - one clock for the 44.1 samplerate family, one clock for the 48 samplerate family, one clock generator that matches the incoming samplerate and a synchronous master clock input via the LVDS / HDMI (I2S/DSD) inputs.
As I have multiple inputs the used clock are selectable (and stored) pr. input.
Thus I use different clocking schemes for the SDTrans, the exaU2I, the SPDIF inputs and other I2S PCM/DSD sources.
 
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I found that either synchronous clocking or clock frequencies that match the played samplerate are a huge improvement compared to 80 / 100MHz clocks that are not working optimal with any samplerate.
Clocks above 100MHz that match the played samplerate are not possible as they would need to be in the 180 - 200MHz area.

I now uses four alternative clocks setups - one clock for the 44.1 samplerate family, one clock for the 48 samplerate family, one clock generator that matches the incoming samplerate and a synchronous master clock input via the LVDS / HDMI (I2S/DSD) inputs.
As I have multiple inputs the used clock are selectable (and stored) pr. input.
Thus I use different clocking schemes for the SDTrans, the exaU2I, the SPDIF inputs and other I2S PCM/DSD sources.

This is a very well approach! It is very logic too...
I have also thinking the same, that the clock have to match the sample rate, but if the chip producer him self was talking about such frequencies as 80, 100Mhz, then I just accepted the idea.
Can you precise what are the clocks frequencies you are using for the respective sample rates you mention?
It is now few weeks since I use the ESS9018 based DAC with 125Mhz clock, and I can say that I`m really aware about the improvement from using 100Mhz clock. I couldn't find yet the right answer/explanation to this (feel like) improvement...

I was thinking about this fact that ESS9018 can today accept clock frequencies as high as 125Mhz. In my opinion it is very possible that with an quite small improvement in chip intern technologies, one could rich that level of a 200Mhz clock frequency for this DAC chip.
It could be just a fantastic improvement for this flagship DAC chip only in this way...
So, it could be an suggestion to ESS people, for the new generation DAC family, if they will/can read this now...
 
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I can see (RayCtech approach) that possible clock frequencies which match f. ex. 44,1 Khz can be: 24,576, 98,304, 122,88 Mhz. Why not use an 122,88 Mhz oscillator?

It looks like intern PLL of ES9018 can well follow a quite large clock frequencies spectre around working/needed frequency... But is much better to meet the chip frequency expectations as accurate as possible...
 
I can see (RayCtech approach) that possible clock frequencies which match f. ex. 44,1 Khz can be: 24,576, 98,304, 122,88 Mhz. Why not use an 122,88 Mhz oscillator?

It looks like intern PLL of ES9018 can well follow a quite large clock frequencies spectre around working/needed frequency... But is much better to meet the chip frequency expectations as accurate as possible...

For the 44.1k family of samplerates:
22.5792 MHz
45.1584 MHz
90.3168 MHz
180.6336 MHz

For the 48k family of samplerates:
24.576 MHz
49.152 MHz
98.304 MHz
196.608 MHz
 
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I think all that we communicated is the answer to our own questions when we asked and ESS responded.

Actually we asked the first time in the ES9008 thread and Dustin answered there.

You should ask them yourselves too if you like. They are quite friendly and ready to give advice.

They never answer me to that simple (email) request for the ES9018 datasheet. Request made after that datasheet was out of their secrecy policy...
 
Many thanks for your correct informations. I see now that I was wrong...

My understanding is that the MCLK requirement is merely;
PCM OSF ON mode: 100MHz > MCLK > 192(=3*64) * fs
PCM OSF OFF mode: 100MHz > MCLK > 24(=3*8) * Fs
(Please remember these multipliers include factor 3. )

Therefore, I guess that the following frequencies (MHz) are valid as "Synchronous MCLK".
For 44.1kHz series: 8.46723, 11.2896, 16.9344, 22.5792, 33.8688, 45.1584, 67.7376, 90.3168, 135.4752, 180.6336
For 48kHz series: 9.216, 12.288, 18.432, 24.576, 36.864, 49.152, 73.728, 98.304, 147.456, 196.608

Among them, I confirmed that frequencies, 22.5792, 45.1584, 90.3168, 24.576, 49.152, 98.304 are effective by myself and "wktk_smile" did for 11.2896 using Chiaki's SDTrans384 transport.
(However, these does not include the factor 3.)
 
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My understanding is that the MCLK requirement is merely;
PCM OSF ON mode: 100MHz > MCLK > 192(=3*64) * fs
PCM OSF OFF mode: 100MHz > MCLK > 24(=3*8) * Fs
(Please remember these multipliers include factor 3. )

Therefore, I guess that the following frequencies (MHz) are valid as "Synchronous MCLK".
For 44.1kHz series: 8.46723, 11.2896, 16.9344, 22.5792, 33.8688, 45.1584, 67.7376, 90.3168, 135.4752, 180.6336
For 48kHz series: 9.216, 12.288, 18.432, 24.576, 36.864, 49.152, 73.728, 98.304, 147.456, 196.608

Among them, I confirmed that frequencies, 22.5792, 45.1584, 90.3168, 24.576, 49.152, 98.304 are effective by myself and "wktk_smile" did for 11.2896 using Chiaki's SDTrans384 transport.
(However, these does not include the factor 3.)


But what about an factor 5? Why factor 3 and not 5?

This version of ES9018 can not more then 133,3 Mhz. But can very well 125Mhz...
If we take (f. ex.) 48Khz sampling frequency and factor 5, then we can have an 122,88 Mhz which is in the upper clock range of this DAC. The same for 44,1Khz, will be 112,896Mhz...
These frequencies match well (by factor 5) with the usual samplings frequencies... It could work well. In my case, it could be better than the clock I use for now (125Mhz).

I will order an 122,896 Mhz oscillator for test with. Else, I`m fully agree that is better way to match exactly the clock with samplings frequency.
 
90.3168 MHz and 98.304 MHz are the highest clock speeds that I have successfully used.

I have tested with clocks above 100 MHz and of course the ES9018 still works, but you get more and more noise as the clock are increased and at some point you also get spurious noise bursts.

It is easy to test what the best optimum clock frequency are in the design you currently use (and the register settings you use):
Connect the outputs of the ES9018 with only a 6dB/oct filter at a high frequency to protect your amplifiers from HF noise and measure the noise the ES9018 outputs with different clock speeds.
You can also simply listen and you will hear the same.
If you use clocks with a enable / disable pin - you can connect several clocks in parallel and enable them one at a time.

It is also possible to use a programmable I2C controlled clock module so you can use the IR remote control to change the frequency over the range 6 MHz to 200 MHz with the used frequency displayed on the LCD display.
I have made such a setup for test purposes...

There is also a big difference in quality between clocks (running at the same speed).
I use only my own custom clocks that are special built to my specifications..
The clocks above 100 MHz needed several production runs to pass my specifications...
 
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But what about an factor 5? Why factor 3 and not 5?

My possible answer is "It's just the minimum integer between 2 and 4".

I think the following frequencies could be regarded as "Synchronous MCLK".
For 44.1 kHz series: 2.8224 MHz x n ( n=3, 4, 5, 6, ... )
For 48 kHz series: 3.072 MHz x m (m=3, 4, 5, 6 ... )

I think it's very important to control and keep constant conditions other than frequency when you discuss clock frequency dependency of sound quality.
Output noise feature of ES9018 depends on its register setting and a phase noise characteristic of asynchronous clock generator effects sound quality.

Coris, Can you figure out all the register values your clock frequency experiments base on?

By the way, the best instrument for changing clock frequency might be like this.(In Japanese)
3GHz ????? CW?????/??????????
 
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Thanks to RayCtech for the last post, good explanations and advices.
Thanks to Bunpei too. A quick answer to you: yes, I keep the other conditions the same, while changing the oscillators. No, unfortunately I can not have any value of the ES9018 registers on this platform I experiment with. As I said before I test on a Oppo BDP95 player. It seems that everything is controlled by software here, so I do not know what about inside the registers and even the registers set-up Oppo used for this ES9018. I will repeat later the same experiments on Buffalo for compare the results.

This time I`ve made some measurements in case of an 100Mhz oscillator (a Buffalo one...), and a standard 125Mhz oscillator (20ppm). The pictures are here to. The measure points are: oscillator output/clk input pin of ES9018, the DAC chip analogue output (before I/V stage), on finally output (RCA).
I have to precise here that I have no any filter between I/V stage and final op amp stage. Only an 10pF paralleled on the I/V resistor and 4pF paralleled on final op amp feedback resistor... I found out that the best sound ever is in this no filters set-up. But this is another discussion...
A little bit increasing in output noise by using 125Mhz is evident, but not substantial... On the finally output (RCA), when using 125Mhz the noise level is quite lower then using an 100Mhz Crystek oscillator.
With this occasion I`ve made again listen/comparing tests with this two oscillators. A big improvement still be in place when using 125 Mhz oscillator. Big increasing in dynamics, even deeper and penetrating bass, a very good spatial separation of the sounds, and wider sound stage. I`m very convinced now about the improvement when using 125 Mhz, even though the measurements are not so evident in this respect... I`m waiting now for the 122,88 Mhz oscillator for test with.
Still not finding the best explanation of all this...
 

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Now I have a question for you and others: have somebody tried to bypass/decoupling ES9018 with 1000µF (ceramic/tantalum) on the AVCC pins (L/R)?

I will not say how it sounds... Maybe somebody else will get curious to try it, and will come here with comments about this experience...

Your idea made me try it! The result is wonderful.
I added 1000 microF/16V Sanyo OS-CON at the output side of AVCC shunt regulator of TPA Buffalo III. The caps bring more powerful bass without losing a high resolution in mid and treble. I'm much satisfied with the result.
Thank you very much for your initial idea!
 
Your idea made me try it! The result is wonderful.
I added 1000 microF/16V Sanyo OS-CON at the output side of AVCC shunt regulator of TPA Buffalo III. The caps bring more powerful bass without losing a high resolution in mid and treble. I'm much satisfied with the result.
Thank you very much for your initial idea!

Adding a large capacitance to the output of a shunt regulator is not a good idea...