Open Source DSP XOs

[TheShaman]

At this point I'm not going to pretend I'm picky! Just save some boards for me..

 

[twest820]

smallest size though, that would be the LT3032

Yeah, that's a rocking little part. Did you have any trouble with the DAPs shorting while soldering it? I keep thinking about using it but haven't quite found a board that wants it yet.

Anyway if someone could desing a board with enough TPS7A4700 chips plus single TPS7A3301 and could order the board with the QNF parts soldered and organize a group buy for it I would order couple of boards.

Make sure it has remote sense, otherwise it's probably not going to deliver datasheet performance from the regulators. If one assumes something like a 150mA digital load for SPDIF recieve, Cortex M4, and the digital side of the DAC that means about 100mA want to return through the grounds of the Vcc and Vee regulators since they're in parallel with the Vdd regulator. Exactly what happens depends on supply filtering and parasitics, but for a fairly good layout and filtering I generally sim a millivolt or so of ripple at the regulator output. This defeats a low noise regulator with local sense as the ground topology forces load regulation to be a couple orders of magnitude worse than the noise.

The 4700 formally supports remote sense via its remote pin but the 3001, 3301, and 4901 do not. This is actually more of a problem for the 4700 as it means interesting things have to be done with the ground of the noise reduction cap to implement differential sense (the datasheet connection of the sense pin in figure 24 is single ended, which only works well if ground bounce is significantly less than the regulator's noise). For the other regulators differential sense is simpler---point of load Vdd/Vcc/Vee and ground taps can be brought back to a voltage divider on the regulator board. I am not, however, entirely sure I trust all this not to oscillate. But it's my suspicion remote sense would tend to mitigate the problem as the regulators will be less prone to servoing each other's grounds, reducing low level oscillation.

It would be interesting to see qusp's schematic for how all this is going to work with the regulators floating.

 

[kamalnegi]

Hi,

I have read your comments about the I2S Communication to the peripheral device. I am beginner in this field and i am thinking if u can help me with Infineon XMC4500 Relax kit spi communication to Peripheral device(9301 controller). I am not able to receive the data from the 9301 controller and i am even not sure that data has been transmitted to the 9301 controller.

Please educate me with the spi communication (transmission and reception) of the infineon xmc4500 relax kit. It will be very helpful if u can provide some sample program and configurations for the kit.

Thanks
Regards
Kamal Negi

 

[mhelin]

Hi,

I have read your comments about the I2S Communication to the peripheral device. I am beginner in this field and i am thinking if u can help me with Infineon XMC4500 Relax kit spi communication to Peripheral device(9301 controller). I am not able to receive the data from the 9301 controller and i am even not sure that data has been transmitted to the 9301 controller.

Please educate me with the spi communication (transmission and reception) of the infineon xmc4500 relax kit. It will be very helpful if u can provide some sample program and configurations for the kit.

Thanks
Regards
Kamal Negi

Haven't got the kit but I would tell you use DAVE and it will generate you enough SPI code. Buy some logic analyzer or scope and watch that you get all clocks and data in and out. Well obviously you should also learn to use the debugger..

 

[abraxalito]

Kudos to Freescale

I think this has to be the first family of Cortex M4s with jellybean pricing - Mouser's showing it at $1.62 in 100s (although no stock currently).

MK10DN32VLF5 Freescale Semiconductor | Mouser

Whilst the Flash memory isn't zero wait state it is equipped with 16k of SRAM, unheard of at this price-point, so probably code can run out of SRAM with no wait states at 50MHz. There's one full duplex I2S port with full buffering and the individual bit clocks on send and receive mean it can be used as an oversampling filter (for example).

 

[steph_tsf]

Cortex M4s - Mouser's showing it at $1.62 in 100s.
Whilst the Flash memory isn't zero wait state it is equipped with 16k of SRAM, unheard of at this price-point, so probably code can run out of SRAM with no wait states at 50 MHz. There's one full duplex I2S port with full buffering and the individual bit clocks on send and receive mean it can be used as an oversampling filter (for example).

With such a low price, one could try one M4 per speaker driver. A three-way active loudspeaker would contain three M4s, each receiving the full audio from I2S, individually filtering the signal, implementing a Power DAC using PWM at 250 kHz followed by a Class-D bridge using N-MOSFETs with bootstrapping for the upper arm. Power supply something like 19V unipolar, for using one or more 90 Watt laptop power supplies. How would I adjust the PWM dead time, for controlling the quiescent current? How would I control the listening volume? Time to get a Sony TA-N88 service manual dating back from 1976. Now that we are in 2013, are there recommendable ICs to be used, for such purpose?

 

[abraxalito]

NXP just announced this new stand-alone debug board for $20 :

NXP Extends Links to LPCXpresso Ecosystem with LPC-Link 2 :: NXP Semiconductors

I'm puzzled because this looks to be something that would replace a J-Link adapter and at a much lower price, so I must be missing something... Its using an LPC4300 family chip so looks to be the cheapest board to date using this chip - could it even be commandeered as a dev board in its own right?

 

[twest820]

Indeed, not at all a bad price for an LPC4357FET256. I suspect NXP/Code Red found a need to be competitive with the ULink2 clones one can get for <$20 for the Keil toolchain. Given NXP stuck analog and digital expansion headers on the board it's presumably intended for dev board as well as debug use. From what Code Red says I'd check back for further developments in a month or two; NXP may be holding off on releasing the pinouts and such until LPCXpresso can drive the board.

What's perhaps more interesting is the improved dual core support in LPCXpresso 5.2.2. Unfortunately the support wiki permissions aren't allowing access to the multi-core project page at the moment. Yay Code Red.

 

[steph_tsf]

NXP just announced this new stand-alone debug board for $20

I must be very tired, and/or completely out of order. Having seen this PCB full of SMDs, realizing how much money NXP must be losing when producing one, realizing the difficulty of producing one myself, I just asked myself why semiconductor companies don't produce microcontrollers that you can embed on a board made by a 3D printer, with all conducting paths and resistors made in just-in-time by the 3D printer. Only a voltage regulator IC and a few capacitors would be needed, that's all. There is a fairly good probability that somebody tried this with Arduino.

 

[abraxalito]

I must be very tired, and/or completely out of order. Having seen this PCB full of SMDs, realizing how much money NXP must be losing when producing one..

Its marketing material. RS lost a lot of money giving its catalogues away for free too - hasn't hurt the overall bottom line as far as I can see. NXP understands this and is pricing accordingly - plenty of other chip manufacturers do not get it and price their boards/software with normal margins. For example only the other day I looked at the pricing of ADI's support materials for its SHARC...

 

[steph_tsf]

This present thread is about Open Source. You may want a kind of poor man's DSP Concepts Audio Weaver, in Open Source.

Audio Weaver? | DSP Concepts

Look the screenshot. You see those blocks and those interconnections ?
Generate the schematic using LTspice. Create parts using LTspice. Interconnect them.

Relying on LTspice, there can't be bells and whistles like user-friendly configuration panels. As example, you'll need to edit the AGC or Limiter parameters using plain text, double-clicking on the part.

Grab the netlist from LTspice, in text format.

Deliver such netlist to a DSP board.

You are done.

Of course you need some DSP bootloader, operating system and scheduler running inside the DSP board. Such is the difficulty.

 

[steph_tsf]

XX100 $ADCL N001 $shift params: n=-8
XX902 N014 $DACL $shift params: n=+8
V1 in 0 AC 1 0
XX900 N012 N013 $db params: dB=-4.3
XX901 N013 N014 $delay params: n=5
XX999 in $ADCL NC_01 $DACL $DACR NC_02 NC_03 $wm8731me
XX905 N017 $DACR $shift params: n=+8
XX903 N015 N016 $db params: dB=-4.3
XX904 N016 N017 $delay params: n=5
XX400 N003 N004 N005 $split
XX200 N001 N002 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX300 N002 N003 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX500 N005 N006 $df2e params: a1=+1.33145199 a2=-0.50455703 b0=+0.04327626 b1=+0.08655252 b2=+0.04327626
XX600 N006 N008 $df2e params: a1=+1.33145199 a2=-0.50455703 b0=+0.04327626 b1=+0.08655252 b2=+0.04327626
XX700 N008 N010 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX800 N010 N012 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX501 N004 N007 $df2e params: a1=+1.33145199 a2=-0.50455703 b0=+0.70900225 b1=-1.41800451 b2=+0.70900225
XX601 N007 N009 $df2e params: a1=+1.33145199 a2=-0.50455703 b0=+0.70900225 b1=-1.41800451 b2=+0.70900225
XX701 N009 N011 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX801 N011 N015 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0

* block symbol definitions
.subckt $shift in out
E1 out 0 in 0 gain={2**n}
.ends $shift

.subckt $db in out
E1 out 0 in 0 gain={10**(dB/20)}
.ends $db

.subckt $delay in out
R2 N003 0 50
R1 N002 N001 50
T1 N002 0 N003 0 Td={n/Fs} Z0=50
E1 N001 0 in 0 1
E2 out 0 N003 0 2
.ends $delay

.subckt $wm8731me MICIN ADCL ADCR DACL DACR LHPOUT RHPOUT
R1 MICIN ADCL 1
R2 MICIN ADCR 1
R3 LHPOUT DACL 1
R4 RHPOUT DACR 1
.ends $wm8731me

.subckt $split IN OUT1 OUT2
R1 OUT1 IN 1
R2 OUT2 IN 1
.ends $split

.subckt $df2e in out
E2 N001 N004 N003 0 {a1}
E3 N004 0 N006 0 {a2}
E4 out N002 checkpoint 0 {b0}
E5 N002 N005 N003 0 {b1}
E6 N005 0 N006 0 {b2}
E1 checkpoint N001 in 0 1
XX1 checkpoint N003 delay_v
XX2 N003 N006 delay_v
.ends $df2e

.subckt delay_v in out
R2 N003 0 50
R1 N002 N001 50
T1 N002 0 N003 0 Td={1/Fs} Z0=50
E1 N001 0 in 0 1
E2 out 0 N003 0 2
.ends delay_v

.param Fs=44100
.ac oct 100 100 10k
* ;-)
* ;-)
.backanno
.end

 

[abraxalito]

Energy Micro has some new M4s - here's a link to the Reference Manual - http://cdn.energymicro.com/dl/devices/pdf/d0233_efm32wg_reference_manual.pdf

While the pricing doesn't look anywhere near as attractive as Freescale, they do include a fair chunk of RAM at the bottom end (32k) and the FPU. There are also 3 USARTs which can be operated in I2S mode - they also support some of the other serial audio formats too Top clock is only 48MHz though.

 

[abraxalito]

Here's an interesting development - ADI, despite having their own IP in the form of the BlackFin (co-developed with Intel) has announced a Cortex M4 SoC : ADSP-CM402F datasheet and product info | ARM Cortex M4 Mixed-Signal Control Processor with Precision 16 bit ADCs in 14x14mm 120 lead LQFP | CM4xx Mixed-Signal Control Processors | Analog Devices

With a top spec'd speed of 240MHz, looks to be the fastest M4 to date. As regards I2S, the DS says these parts have '3 half-Sports' which can be configured into I2S mode. Perhaps the 'half' means only half duplex? Chip prices not yet released but the eval boards are $200-$300, the more expensive one coming with a Segger J-link.

 

[twest820]

Blackfin is 16 bit so 32 bit processing takes quite a few clocks. The 32 bit data path and 80 bit MAC on the SHARCs is a more proper competitor to the M4's 32 bit data path and 64 bit MAC. A DSC like the M4 tends to be faster on IIR and DSPs like the SHARC faster on FIR and even fairly low normalized frequency biquads don't benefit from the extra 16 bits in the SHARC MAC. So it's logical diversification on the DSP side, greater flexibility of a microcontroller aside.

Each SPORT has SCLK, WCLK, and two data lines which can operate in either direction. From a quick look in the neighborhood of page 23-27 it sounds like the data lines are independent of each other. So with the four half sports on the 176 pin LQFP one could probably do one I2S in and three I2S out for, say, SPDIF receive and three way XO. Or USB in and four way XO.

If one opts for a part compatible with the SPORTs packed I2S format then IO is a non-issue for most scenarios. The CS4365 and CS4385 DACs and CS42526 and CS42528 codecs come to mind.

Interesting offering. Given the right tools and pricing it could be a viable alternative to NXP's LPC4300s for the mainline case where only one "codec"'s worth of IO is needed.

 

[Trevor White]

Blackfin is 16 bit so 32 bit processing takes quite a few clocks. The 32 bit data path and 80 bit MAC on the SHARCs is a more proper competitor to the M4's 32 bit data path and 64 bit MAC. A DSC like the M4 tends to be faster on IIR and DSPs like the SHARC faster on FIR and even fairly low normalized frequency biquads don't benefit from the extra 16 bits in the SHARC MAC. So it's logical diversification on the DSP side, greater flexibility of a microcontroller aside.

Each SPORT has SCLK, WCLK, and two data lines which can operate in either direction. From a quick look in the neighborhood of page 23-27 it sounds like the data lines are independent of each other. So with the four half sports on the 176 pin LQFP one could probably do one I2S in and three I2S out for, say, SPDIF receive and three way XO. Or USB in and four way XO.

If one opts for a part compatible with the SPORTs packed I2S format then IO is a non-issue for most scenarios. The CS4365 and CS4385 DACs and CS42526 and CS42528 codecs come to mind.

Interesting offering. Given the right tools and pricing it could be a viable alternative to NXP's LPC4300s for the mainline case where only one "codec"'s worth of IO is needed.

Don't both parts use 16 bit multipliers and SIMD to execute a 32 bit multiply ? Neither execute a 32 bit multiply in one clock cycle.

 

[abraxalito]

From ARM's Technical Reference Manual for the M4 :

 

[Trevor White]

From ARM's Technical Reference Manual for the M4 :

Is that for a 16 bit multiply or 32 bit ? Apparently its floating point performance apparently is not that good,

DSP operations can use either floating point or fixed point format. The Cortex M4 core has optional hardware support for 32 bit floating point, but is not optimized for DSP algorithms and too slow for most DSP applications.

 

[twest820]

Trevor, arm_biquad_cascade_df1_q31 and arm_biquad_cas_df1_32x64_q31 are built around SMLAL. You can find specifics in the links and a bit more context on the DSP requirements in this post, though the questions you're asking would be best answered by spending some time with the instruction set and DSP library documentation for the respective processors.

A 200ish MHz single M4 core more or less by definition can't compete with a 450MHz dual core SHARC, much less the TigerSHARCs. But, as I've remarked earlier on this thread, an M4 around 75MHz is sufficient for pretty rich IIR based XO and EQ on 24/44.1 audio---more typical configurations could run in 25MHz or less. At full clock the faster M4s are comparable to the low end SHARCs used in things like Peavey's Vypyr modeling amplifiers and a pair of them isn't that far off the dual Blackfins Fractal Audio had in the original AxeFX. So the bang for the buck on an M4 that's $9 or less in DIY quantities and uses a free development environment with $20 or less of debug hardware is high compared to $4k or so entry cost for SHARC tooling. I'm curious to see where Analog positions the M4 along the SigmaDSP to SHARC continuum; wouldn't be entirely surprising if the M4 ends up being a SigmaDSP replacement.

 

[abraxalito]

Is that for a 16 bit multiply or 32 bit ?

32bit which can generate either a 32bit or 64bit result. There's no 16bit multiply though from memory there might be a dual (i.e. in parallel) 16bit multiply instruction.

Apparently its floating point performance apparently is not that good,

Where did you get your quote?