Open Source DSP XOs

[abraxalito]

Originally Posted by steph_tsf

I very much like the AM335x features, but at this stage I get somewhat discouraged, seeing that "more may mean less".

That was indeed my initial response to the datasheet on that part. Its so much more that do I really want to invest the time learning to get the best out of it? Too big an investment of time I feel, so I'm going to stick with the Cortex M for now because it does suit my needs well.

[Trevor White]

Originally Posted by steph_tsf

Right. You don't want to see the full picture. Show me an ADC and a DAC combination working at 44.1 kHz or 48 kHz that is delivering the required square wave in / square wave out. Without staircases. Without aliasing. If you can show this, I will revise my opinion, and will consider that daddy's DSP operating at 44.1 kHz or 48 kHz remains a valid foundation.

why operate at 48K ? What not operate at 96KHz or 192K at 24 bit ??

regards
Trev

[steph_tsf]

Originally Posted by abraxalito

Run the squarewave into an ADC sampling at say 32X - so the ADC needs to be running at 1.4MHz, not a major problem with today's technology. It wouldn't need to be the full 16bits either because we're reducing the bandwidth. This ADC can have a fairly gentle bessel AAF which does not generate ringing. Then downsample to 44k1 using a minimum phase FIR filter. On the output do this in reverse. You'll get overshoot and ringing because the bandwidth reduction is severe but you'll avoid staircases and aliasing.

What I'm suggesting is to run the squarewave into an ADC sampling at 32x - so the ADC needs to be running at 1.536 MHz, not a major problem with today's technology. It wouldn't need to be the full 16 bits either because we're reducing the bandwidth. This ADC would have a 8th order Bessel lowpass AAF -3dB at 34 kHz which does not generate ringing. Then downsample to 192 kHz using a FIR filter emulating a 16th order Bessel lowpass -3dB at 34 kHz. Stay 192 kHz in the storage and audio processing. For the output, use a non oversampling DAC operating at 192 kHz, and analog lowpass the signal using a 8th order Bessel reconstructing lowpass -3dB at 34 kHz. You'll get no overshoot, no preshoot, no ringing, only tiny staircases at -70 dB, that you may eradicate by increasing the order of the DAC reconstructing lowpass.

Now realizing this, an nice improvement would be to define the global filtering function (ADC, FIR, DAC) as a 32nd order Bessel -3dB at 34 kHz, then decompose such function in three segments : 8th order for the DAC, 16th order for the FIR, and 8th order for the DAC. None of the three are Bessel anymore, if taken individually, but what matters is that when taken together, they form a 32nd order Bessel -3dB at 34 kHz.

[steph_tsf]

Now the poor man's version of what got suggested in the above post. Running at 96 kHz instead of 192 kHz and defining the global lowpass function as a 32nd order Bessel -3dB at 17 kHz instead of 34 kHz.

Wondering if a NOS DAC like a TDA1545 could be persuaded to run at 96 kHz. If yes, the suggested poor man's system may deliver some interesting results. May try something recent like T.I. DAC8562 or DAC8563, with a Glitch Energy of only 0.1 nV-s.

Any suggestion for a poor man's ADC comfortably running at 768 kHz, say 14 bit resolution ? T.I. ADS7945 or ADS7946 perhaps ?

[abraxalito]

Originally Posted by steph_tsf

Wondering if a NOS DAC like a TDA1545 could be persuaded to run at 96 kHz.

Easy job - the datasheet specs are shown for a sample rate of 192kHz, it will go up to 384k.

Any suggestion for a poor man's ADC comfortably running at 768 kHz, say 14 bit resolution ? T.I. ADS7945 or ADS7946 perhaps ?

ADI has a very nice quick search function for ADCs now, it turned up this one which is the cheapest 14 bit part with enough speed - $5 in volume. THD is -96dB @ 100kHz in. SNR 79dB in 500kHz bandwidth translates to 91dB in 30kHz.

http://www.analog.com/static/importe...ets/AD7264.pdf

[abraxalito]

Eat your heart out STM, your 'fastest M4' at 168MHz has been easily bested by NXP

NXP boosts LPC43000 to 204MHz, hits the shelves

NXP are saying the bottom of the range asymmetric dual-core M4/M0 part will be under $4 in 10k.

Updated datasheet here: http://www.nxp.com/documents/data_sh...0_30_20_10.pdf

[s3tup]

As for the software for the DSP manipulations - i'm working on something related to this...

Graphic Filter Designer

The idea is to simulate the analog circuit in digital domain with a PC, and then "compile" it to different targets
- Analog boards
- DSPs
You'll be able to design the filters for DSPs alone, if you use digital-only filters (delays, or non-textbook biquads or whatever else. No FIRs... )

I've got signal chaining, control points, biquad graphing, and a loop of control point>change of parameters of filter>generation of biquad parameters>chaining of different biquads>graphing in a single mouse stroke.
Graphing of FR is ready too


+ FFT with windowing functions.

Windows only...

[steph_tsf]

Originally Posted by s3tup

I've got signal chaining, control points, biquad graphing, and a loop of control point>change of parameters of filter>generation of biquad parameters>chaining of different biquads>graphing in a single mouse stroke.
Graphing of FR is ready too. Also FFT with windowing functions. Windows only.

Wonderful ! Would be nice to have a crossover signal flow like the one I've attached. Is it feasible ?

[steph_tsf]

I had a look to the newest PIC32MX1xx and PIC32MX2xx from Microchip. Their two SPi do now feature an I2S mode for interfacing audio CODECs and DACs.

Quite bizarre is that those new chips now materialize the low-end range of the PIC32 product family. Those new chips only support a 40 MHz clock. Only 2.25 eur from Mouser, dropping to 1.56 eur when in 150 qty. They have revised the Slave_Select pin management of their SPI, enabling it to operate as LRCK for implementing I2S. As slave and as master. There is an explicit MCLK signal, internal. There are now 5 Special Function Registers associated to SPI (beforehand, there were only 4 such registers). SPIxCON2 is the new SPi Special Function Register, dealing with the audio modes (I2S) of the SPi.

Such PIC32MX1xx and PIC32MX2xx can be used as crossover building blocks.
One PIC32MX2 as pre-processor (possibly with USB2 audio input, possibly asynchronous), using one SPi in the I2S mode, and one SPi for controlling the DACs volumes.
Two PIC32MX1 exploiting the same pre-processed signal, acting as crossovers, each outputting two I2S lanes.
You get a stereo 4-channel xover executing 32*32+64=64 math.
Something a Freescale DSP56K or an Analog Devices ADAU1401A can't do.

There would thus be three PIC32 chips on the xover board.
I own a Microchip ICD3 debugger.
Can I program and debug all three chips individually, from a single debug connector ?
Is there something like the ARM "SWD multidrop" debug protocol, in the Microchip world ?

[steph_tsf]

Originally Posted by abraxalito

NXP are saying the bottom of the range asymmetric dual-core M4/M0 part will be under $4 in 10k.

Would this mean an Embedded Artists LPC43xx LPCXpresso Board at 20 eur plus tax ?