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Old 2nd December 2011, 11:21 AM   #61
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Originally Posted by rsdio View Post
EDIT: Upon rereading this, I guess maybe you're saying that the advantage is the 64-bit aspect, not the fixed point aspect. I usually work with a DSP that has 40-bit and 80-bit accumulators, so at first I did not see your point.
Knowing Steph I'd say that his point was that in comparison to the DSP56k which he has experience of, a 64-bit accumulator is an advantage, yes. 32bit coefficients are called for in lower frequency bi-quads such as might be needed for a subwoofer XO in order to maintain adequate noise performance. 32 bit floating point I don't feel would be a very good choice for a crossover filter seeing as its precision is 24bits.

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I guess that when you press a general purpose processor into DSP work, you typically have to deal with smaller 32-bit registers, but with special purpose DSP chips you have the advantage that the processor is already designed with enough bits of overhead to handle calculations properly. This suggests to me that a great option would be one of the Texas Instruments chips that combines both an ARM and TMS320 DSP in the same package. Perhaps overkill for a crossover, but certainly the DSP will have appropriate instructions and registers for filters.
ARM Cortex-M supports some instructions that concatenate two registers as far as I'm aware - I've used the (M3) load- and store- double instructions myself. I haven't studied the M4 DSP extensions in detail yet though. The M3, although not designed as a DSP does have a (rather slow) double multiply accumulate.
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Old 2nd December 2011, 11:59 AM   #62
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Originally Posted by rsdio View Post
I have worked with the TI McBSP ports and have studied the McASP ports. I would suggest that the most you could hope for with up to two McASP ports is to implement up to two I2S lanes. If you'd care to explain how a single McASP port can implement two parallel I2S lanes, or even if you can just point to a specific page in the Texas Instruments documentation which gives any clue as to how this could be pulled off, then I would be seriously interested in learning a new technique.
The AM335x datasheet (doc number SPRS717 –OCTOBER 2011) says "Up to Four Serial Data Pins per McASP". See page 69 : Table 2-53. McASP/MCASP0 Signals Description. They are all laid out. Four data pins per McASP port, that you can individually define as input or output. Same as DSP56K.

Last edited by steph_tsf; 2nd December 2011 at 12:11 PM.
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Old 2nd December 2011, 01:53 PM   #63
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Originally Posted by rsdio View Post
I guess maybe you're saying that the advantage is the 64-bit aspect, not the fixed point aspect. I usually work with a DSP that has 40-bit and 80-bit accumulators, so at first I did not see your point. I guess that when you press a general purpose processor into DSP work, you typically have to deal with smaller 32-bit registers, but with special purpose DSP chips you have the advantage that the processor is already designed with enough bits of overhead to handle calculations properly. This suggests to me that a great option would be one of the Texas Instruments chips that combines both an ARM and TMS320 DSP in the same package. Perhaps overkill for a crossover, but certainly the DSP will have appropriate instructions and registers for filters.
Indeed. When you optimize the way an IIR BiQuad is interfacing the multiplier-accumulator, when you realize that the IIR storages contain truncated data, and when you realize how such truncated data actually gets recirculated and amplified in the two recursive paths, then you realize that the 32*32+64=64 fixed point math delivered by a 5.00 dollar ARM chip is surpassing all 24/56 bits fixed point systems and all 28/56 bits fixed point systems. A 40/80 bits system like SHARC looks better. In theory. What is the storage width in a SHARC ? If the SHARC storage width is only 32-bit, it means that you only can multiply a 32-bit number with a 32-bit number, thus there is no advantage for using a so-called 80-bit SHARC processor for IIR BiQuads. The exact same 32-bit truncated data gets recirculated and amplified in the two recursive paths of your IIR.

Try a 2nd order Linkwitz Transform at 45 Hz basing on a IIR BiQuad, using a 96 kHz or 192 kHz sampling frequency. However looking high-end today, it will soon become mainstream. Linkwitz Transforms are known and used in analog technology since decades. They exhibit a -140dB distorsion and noise floor using modern opamps, when operated at a constant line level (meaning that the volume pots need to be located after the crossover). What we want is to get the same performance level from digital, with some added flexibility. The bad news is that all 24/56 bits fixed point systems and all 28/56 bits can't and won't adjust to such requirement. Only the 32*32+64=64 fixed point math delivered by ARM has the required flexibility. And it costs less. And it takes less current. The SHARC looks extremely expensive, and no improvement over ARM because of the same 32 bit storages as the ARM. This is in a IIR context.

Take any "good old" 44.1 kHz and 48 kHz system, present an analog square wave at 1 kHz, digitize it using a decent ADC, store it, and output it back in analog using a decent DAC. What do you get ? A square wave again ? Not at all. What you get back is an ugly wave exhibiting ringing, overshoot, and preshoot.

What did you expect ? A gentle, rounded-edge square wave ? Clearly, personally, what I did expect was a square wave like after getting filtered by a 8th-order lowpass Bessel at 20 kHz. Who delivers this today ?

We are not talking about daddy's DSP like the early 3M or SoundStream digital recording and mastering systems in the early eighties. We are 30 years later, with cleaner and more demanding expectations.

We are not interested in reproducing CDs that have been mastered using daddy's DSP techniques. We want to clarify the whole recording process, mixing process, and mastering process, ensuring that a 1 kHz square wave at the input, shows as a 1 kHz square wave at the output, just before the power amps in case there is no DSP inbetween. This is the aim of 96 kHz and 192 kHz audio DSP. I feel this is a basic, gentle requirement in 2011.

So logically, 96 kHz or 192 kHz for adding DSP looks mandatory. Logically, such 96 kHz or 192 kHz system must execute a Linkwitz Transform as low as 45 Hz with less than -140 dB distorsion and noise floor.

DSP means flexibilituy, so logically, such 96 kHz or 192 kHz system needs to be powerful enough for allowing a high-resolution gain and phase linearization of each transducer individually, thanks to 128-tap or 512-tap FIRs. In a crossover, controlling the phase of the transducer is mandatory. With IIRs you cannot tailor the gain and the phase independently at your will. You get more freedom with a FIR.

This being said, a powerful room equalizer may be desirable at the input, for guaranteeing a 2 dB corridor between 35 Hz and 17 kHz. Such room equalizer would require a 512-tap FIR.

Having realized this, you understand that your next audio DSP chip needs to be clockzed around 400 MHz, and provide a single-cycle 32*32+64=64 fixed point math, with 32 bit storages.

For doing the crossover kernel, you can use any technique, IIR or FIR. With IIRs you can emulate textbook crossovers like a Baekgaard (a state-variable IIR BiQuad delivering the bass, mid and high), a Linkwitz-Riley, a Lipshitz-Vanderkooy delay-compensated, etc ... With a FIR in the crossover kernel, you can emulate textbook crossover (that's not efficient from a computing point), or you can design extremely steep crossovers exhibiting 100dB/octave slopes, and tailor the phase response at your will (that's a new area we should investigate).

Steph
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Old 2nd December 2011, 11:38 PM   #64
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Originally Posted by steph_tsf View Post
The AM335x datasheet (doc number SPRS717 –OCTOBER 2011) says "Up to Four Serial Data Pins per McASP". See page 69 : Table 2-53. McASP/MCASP0 Signals Description. They are all laid out. Four data pins per McASP port, that you can individually define as input or output. Same as DSP56K.
Thanks for the hint. The real meat is in SPRUH73A, where details are given in how the clock signals are shared for each data I/O pin and how separate EDMA channels can be used for the separate I2S streams.
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Old 3rd December 2011, 12:29 AM   #65
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Originally Posted by rsdio View Post
Thanks for the hint. The real meat is in SPRUH73A, where details are given in how the clock signals are shared for each data I/O pin and how separate EDMA channels can be used for the separate I2S streams.
Unfortunately SPRUH73A cannot be downloaded at the moment. Fortunately there is still SPRU041J concerning the TMS320C6000 DSP. Please let us know when SPRUH73A (or a new version) can be downloaded.

Update : SPRUH73A is still there, but incorrectly referenced by all AM335x T.I. webpages. Go to http://www.ti.com/ webpage. Enter "SPRUH73A" in the search box. The first seach result is the good one. You can download SPRUH73A from http://www.ti.com/lit/ug/spruh73a/spruh73a.pdf. McASP description to be found on chapter 22 page 4190.
Hope T.I. silicon is less chaotic than their webpages.

Last edited by steph_tsf; 3rd December 2011 at 12:45 AM.
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Old 3rd December 2011, 12:34 AM   #66
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Originally Posted by steph_tsf View Post
Take any "good old" 44.1 kHz and 48 kHz system, present an analog square wave at 1 kHz, digitize it using a decent ADC, store it, and output it back in analog using a decent DAC. What do you get ? A square wave again ? Not at all. What you get back is an ugly wave exhibiting ringing, overshoot, and preshoot.

What did you expect ? A gentle, rounded-edge square wave ? Clearly, personally, what I did expect was a square wave like after getting filtered by a 8th-order lowpass Bessel at 20 kHz. Who delivers this today ?
Steph
The ringing comes from the oversampling filters used in the sigma delta DACS and ADC's. It has got nothing to do with the DSP. If you directly connected a sigma delta ADC to a sigma delta DAC without any intervening processing you would get exactly the same ringing on the square wave
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Old 3rd December 2011, 01:10 AM   #67
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Originally Posted by steph_tsf View Post
Hope T.I. silicon is less chaotic than their webpages.
Alas, they have so many complex DSP chips that there is quite a bit of chaos. Look on their E2E Forum and Wiki and you'll find some of the strange silicon bugs that I've uncovered. If you actually utilize all of the various peripherals and features then there's a chance you might run into a little chaos. I don't think any other manufacturer of esoteric embedded chips has silicon without errata, though.
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Old 3rd December 2011, 01:14 AM   #68
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Originally Posted by Trevor White View Post
The ringing comes from the oversampling filters used in the sigma delta DACS and ADC's. It has got nothing to do with the DSP. If you directly connected a sigma delta ADC to a sigma delta DAC without any intervening processing you would get exactly the same ringing on the square wave
Right. You don't want to see the full picture. Show me an ADC and a DAC combination working at 44.1 kHz or 48 kHz that is delivering the required square wave in / square wave out. Without staircases. Without aliasing. If you can show this, I will revise my opinion, and will consider that daddy's DSP operating at 44.1 kHz or 48 kHz remains a valid foundation.
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Old 3rd December 2011, 01:30 AM   #69
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Originally Posted by rsdio View Post
Alas, they have so many complex DSP chips that there is quite a bit of chaos. Look on their E2E Forum and Wiki and you'll find some of the strange silicon bugs that I've uncovered. If you actually utilize all of the various peripherals and features then there's a chance you might run into a little chaos. I don't think any other manufacturer of esoteric embedded chips has silicon without errata, though.
Indeed I went on the E2E Forum and Wiki. It's quite a mess over there with different kind of people mixing, some having trouble with the booting schemes, others asking how to port Android on the AM335x, and others like you presumably wanting to regain bare metal, hence uncovering bugs.

I very much like the AM335x features, but at this stage I get somewhat discouraged, seeing that "more may mean less".

If T.I. could deliver more support software like the one they have regarding the pin configurator, that would be fantastic.

I can't believe that in 2011, more than 30 years with microcontroller, there is no global digital standard describing the registers, some recommended configurations, in an interactive way possibly using XML. You would configure a chip, define the boot sequence, configure the pinout and the peripherals, by loading an XML parser eventually featuring a graphical user interface. This should be incorporated in the software debugger, for generating the associated initialization code.
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Old 3rd December 2011, 01:45 AM   #70
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Quote:
Originally Posted by steph_tsf View Post
Right. You don't want to see the full picture. Show me an ADC and a DAC combination working at 44.1 kHz or 48 kHz that is delivering the required square wave in / square wave out.
I do find myself questioning why squarewave performance is relevant to audio. But sure its possible - but only using oversampling.

Run the squarewave into an ADC sampling at say 32X - so the ADC needs to be running at 1.4MHz, not a major problem with today's technology. It wouldn't need to be the full 16bits either because we're reducing the bandwidth. This ADC can have a fairly gentle bessel AAF which does not generate ringing. Then downsample to 44k1 using a minimum phase FIR filter. On the output do this in reverse.

You'll get overshoot and ringing because the bandwidth reduction is severe but you'll avoid staircases and aliasing.
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