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Old 19th October 2011, 12:25 PM   #41
vdB is offline vdB  Netherlands
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One way to approach the software side is to define an XML schema (XSD) describing the supported XO building blocks (channels, filters), their configuration options, and the ways they can, and hence cannot, be combined. XML documents that match it can serve as the files describing your XO design, which can be saved, shared with others etc.

The essential part then is to find a way to translate these XMLs to instruction sets that can be executed by the DSP board, and preferably vice versa as well. Not sure if the latter is very feasible though.

One advantage is that it would turn the ultimate goal of the GUI's XO design section into one of manipulating the contents of an XML file. Especially for a POC this part could temporarily be replaced by any tool that is capable of doing this.

Also, it could simplify the task of converting XO/filter designs made in other tools, as one wouldn't have to worry about the target DSP's internals. Valid XML would be all the converter has to produce.

Anyway, just my two cents...
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Old 28th October 2011, 05:58 AM   #42
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For anyone who's been shying away from Cortex M0 as DSP because the packages aren't quite DIY-friendly enough, this will come as welcome relief :

NXP Cortex-M0 Microcontrollers in High-Volume TSSOP and SO Packages Target 8/16-bit Applications :: NXP Semiconductors

NXP I reckon is the DIYers friend - who on earth apart from a DIYer would be designing with a DIL28 0.6" pitch package MCU? (Datasheets weren't available last time I checked.)
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Old 8th November 2011, 07:04 AM   #43
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More details from ARM on the DIL Cortex M0s :

Hey Hobbyists, dust off your breadboards - DIP package is back; - ARM Community
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Old 13th November 2011, 11:39 PM   #44
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NXP now has the updated datasheet which includes the 20- and 28-pin M0 parts. Oddly though if you go looking for it on the M0 microcontrollers section, you hit a 404 error

http://www.nxp.com/documents/data_sh...1_12_13_14.pdf
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Old 15th November 2011, 02:16 AM   #45
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Here's an illuminating chat with an EDA guru about the way computing is being constrained to move in the direction of lower power - of course, using ARM.

Gary Smith EDA talks about the state of the ARM industry ARMdevices.net
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Old 15th November 2011, 08:51 PM   #46
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I saw the video showing Gary Smith in post #45 above. Liked the idea of "instant on, normally off" computing. Liked the idea of the current drain becoming the most important specification. Got amazed when he described a 400 MHz clock as ideal nowadays, and Gigahertz clocks to be considered as a joke. I liked the idea of the PC reducing to a niche, in front of mobile phones, tablets and new generation computing devices becoming mainstream. However, I could not catch the objection about the Cloud at 9:22 in the video. Can someboby explain it to me ?

Where do we go, actually ?
A quad core Cortex-A7 accompanied by a PowerVR SGX, both clocked at 400 MHz nominal, that you can push to 800 MHz ?

Worth looking at BeagleBone, basing on a TI AM3358 ARM, currently single core Cortex-A8. http://www.ti.com/product/am3358
Two Multichannel Audio Serial Ports Supporting Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and similar Formats.
Expected retail price of $89.
Will execute 2048-tap FIRs in stereo at 96 kHz with 32x32+64=64 math ?

Last edited by steph_tsf; 15th November 2011 at 09:18 PM.
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Old 15th November 2011, 09:24 PM   #47
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I've heard this idea about mobile computing taking over but the fact is for serious computationally intensive applications, as things get more efficient, there will still be high demand for whatever can be done with a couple hundred watts. Some people don't realize that the world is not advancing simply by browsing the internet and streaming some video.
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Old 15th November 2011, 10:20 PM   #48
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$5 Cortex-A8 SoC aims to take on ARM9 in the embedded market - News - Windows for Devices
It says there will be T.I. AM335x chips (presumably not equipped with the PowerVR SGX) costing as little as $5 in volume.
Add some Flash, run from internal RAM, and you get more computing power than a DSP56725, and more precison thanks to the 32x32+64=64 math.
On the other hand, the DSP56725 has a better audio DSP connectivity, featuring four I2S lanes.
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Old 15th November 2011, 11:19 PM   #49
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What is the STM32 F4 price, in volume ?

The STM32 F4 is a 90 nanometer Cortex-M4 clocked at 168 MHz featuring :
- Up to 1 Mbyte of Flash memory
- Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM
- Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories
- Up to 3 I2C interfaces (SMBus/PMBus)
- Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)
- Up to 3 SPIs (37.5 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock
- 2 CAN interfaces (2.0B Active)
- 1 x SDIO interface

The two full-duplex I2S enable building an inexpensive "parallel" xover like analog xovers are (thanks abraxalito for the idea).

Put one F4 as stereo equalizer and/or room equalizer.
Put one F4 as stereo sub & bass stereo channels processor.
Put one F4 as stereo medium & tweeter channels processor.

Is there a single-cycle 32x32+64=64 multiplier-accumulator ?
If yes, three F4 chips would deliver 504 DSPMips combined.
There could be a 512-tap FIR in the room equalizer.
There could be a 256-tap FIR in each channel, for individually equalizing the speaker drivers gain and phases.
Okay, I confess a DSP56725 delivering 500 DSPMips, only costing $6.05, also can do this.
Here, with the F4, you would execute 32x32+64=64 math instead of 24x24+48=48 math.

Attached is a design proposal. Anyone interested ?
Attached Images
File Type: jpg 3F4 xover.jpg (162.2 KB, 514 views)
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Old 16th November 2011, 12:08 AM   #50
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Quote:
Originally Posted by steph_tsf View Post
I could not catch the objection about the Cloud at 9:22 in the video. Can someboby explain it to me ?
That's also the only part of the video that left me confused. He was talking about homogenous and heterogenous computing and he implied that the cloud model was the former rather than the latter. I couldn't make the jump that he was seeing - to me the cloud is heterogenous - its isomorphic to ARM's big.LITTLE with the LITTLE in your hand and the big in the cloud.
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