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Old 24th October 2013, 01:58 AM   #481
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This talk of codec strapping got me curious so I got to checking back on things. Unsurprisingly, it remains there are no suitable Arduino or Raspberry Pi boards (unsurprisingly, Raspy Fi is still USB out). The BeagleBone Black brings out a full set of mcasp0 pins from its AM3359 to the expansion headers but unfortunately fails to do so in a way that's I2S friendly. Specifically, use of all four AXR pins requires IO mode 3 or 6. But from what I can tell the only mode that sort of works with the user accessible pins on the Black is mode 0, which yields one data line out to the expansion headers whose clocks are shared with the I2S over to HDMI.

I2C and clocks are on the expansion headers, though. So, given a DAC with a one line mode, one could use a Black DAC cape to enable USB -> DSP XO + EQ -> DAC. But not SPDIF -> DSP -> DAC as there's no support for a second data line in mode 0. Enough nets on the board go through resistors one could probably blue wire something up for mode 3 or 6 given a pair of hot tweezers but, eh, it's not something I consider worth the hassle.
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Old 24th October 2013, 02:35 AM   #482
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hi twest820, thinking about an "audio cape" for the Embedded Artists LPCLINK2?
The Rev. C schematics are here : http://www.embeddedartists.com/sites...k-II_Rev_C.pdf
The CPU is a LPC4320, the datasheet says it features Cortex-M4 + Cortex-M0 + SGPIO.
Check J3, J4 and J9 on LPCLINK2 schematic, page 6.
Basically, Embedded Artists say LPCLINK2 it is a standalone debug probe, designed to connect on Embedded Artists LPCXPRESSO boards as targets.
However, J3, J4 and J9 appear to be designed, for LPCKINK2 becoming a target equipped with a "cape" dealing with SGPIO, SSP1, UART2 and I2C.
Now comes the question : how would you debug this? Get a second LPCLINK2 used as debug probe, outputting the SWD lines to the second LPCLINK2 used as target?

Last edited by steph_tsf; 24th October 2013 at 03:02 AM.
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Old 24th October 2013, 03:09 AM   #483
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Quote:
Originally Posted by twest820 View Post
This talk of codec strapping got me curious so I got to checking back on things. Unsurprisingly, it remains there are no suitable Arduino or Raspberry Pi boards (unsurprisingly, Raspy Fi is still USB out). The BeagleBone Black brings out a full set of mcasp0 pins from its AM3359 to the expansion headers but unfortunately fails to do so in a way that's I2S friendly. Specifically, use of all four AXR pins requires IO mode 3 or 6. But from what I can tell the only mode that sort of works with the user accessible pins on the Black is mode 0, which yields one data line out to the expansion headers whose clocks are shared with the I2S over to HDMI.

I2C and clocks are on the expansion headers, though. So, given a DAC with a one line mode, one could use a Black DAC cape to enable USB -> DSP XO + EQ -> DAC. But not SPDIF -> DSP -> DAC as there's no support for a second data line in mode 0. Enough nets on the board go through resistors one could probably blue wire something up for mode 3 or 6 given a pair of hot tweezers but, eh, it's not something I consider worth the hassle.
Thanks for that I've been toying with the idea of BB(Black)+DIX9211 (I've got an old white BB here at the moment) and need to dig through the pin outs a bit more thoroughly yet to see how that'll work, I'm still pretty new to embedded dev and the datasheets have taken some work to get my head around.

i2s interface on the fpga + linux drivers for a zynq chip still seems the most robust idea though, especially for multichannel i2s.
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Old 24th October 2013, 03:17 AM   #484
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Originally Posted by steph_tsf View Post
However, J3, J4 and J9 appear to be designed, for LPCKINK2 becoming a target equipped with a "cape" dealing with SGPIO, SSP1, UART2 and I2C.
[Edit for steph's edit.] Only if one uses a generous interpretation of designed. There's no SGPIOs and only part of an I2S route to J9. With only two SGPIO's J4's not useful for audio on its own and the TRACEDATA pins on J8 are only available as SGPIOs if you hack the debug connector to 10 pin Cortex from 20 pin JTAG. J3 has three SGPIOs, I2C, and CLKIN. One could biamp from J3+J4 and triamp/quadamp from J3+J4+J8 but I wouldn't consider either option particularly attractive.

Last edited by twest820; 24th October 2013 at 03:27 AM.
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Old 24th October 2013, 03:24 AM   #485
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Originally Posted by hochopeper View Post
need to dig through the pin outs a bit more thoroughly yet to see how that'll work
For some reason DIYA's no longer allowing spreadsheets to be attached to posts but if you PM me your email I'll send you my BeagleBone Black spreadsheet extracted from the csv files underlying TI's PinMux tool. Then you can plug the Black's expansion header pins into PinMux and see the mcasp0 IO set violation light up.
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Old 24th October 2013, 11:53 AM   #486
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Xmos have got a new product today, designed in partnership with Silicon Labs Cortex M3 SoC with their programmable logic cores on one chip.
XMOS creates the next wave in programmable system-on-chip products | XMOS
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Old 25th October 2013, 01:43 AM   #487
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Yeah, I was looking at those last night. The M3 addition certainly moves them closer to this thread's definition of open and makes sense from the standpoint of not needing to dedicate an XMOS core to IO. But I find it's hard to get excited about the XMOS cores. 8 16 bit-ish cores at 400MHz to do 20 biquads at 48k is the equivalent of a single M4 at something like 75MHz. And the parts cost around twice as much as M4s for comparable oomph. Fairly woeful compared to a Blackfin as well. On the plus side the tools are free, the eval boards are mostly pretty inexpensive, and there's good LQFP availability.
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Old 25th October 2013, 03:02 AM   #488
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Interesting - but hard work cutting through the marketing gloss to uncover what's really going on. For example 'programmed completely in C-code'. When I looked at XMOS they had their own version of C called 'XC' - which includes extensions to normal C to handle the concurrency. If this is still the case then this claim is at best misleading as the ARM version of C doesn't support those concurrency constructs. How will developing with two incompatible versions of C pan out I wonder?

Lower down there's the claim that the new SoC will have '8 32-bit processors' which is immediately contradicted by '7 xCore logical cores plus one ARM M3' (italics my own). A logical core and a physical processor look to me to be quite different beasts. Even Intel, rather notorious for reality stretching in its marketing, doesn't say a logical core counts as a physical CPU when promoting its hyperthreading feature. Then the future products with '6-core and 8-core' don't really make sense as they've just described the first one which has already 8 cores.

An interesting thread (pun intended) running through this brief is the use of 'energy' rather than power. Perhaps inherited from Energy Micro which Silicon Labs purchased in the summer ($170m). This rather makes me wonder that the power consumption is nothing to get excited about, what their USP is that it can be put to sleep most of the time with low overhead and low leakage current.
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Old 25th October 2013, 03:35 AM   #489
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Yeah I'm just dipping my toe in the water and seeing what's around, this thread is a great learning ground for these things, thanks to everyone who has contributed, I've learned stacks! I've got an original BeagleBone and a Parallela on pre-order (Xilinx Zynq 7020 + 16core Adapteva Epiphany III) that I'm hoping to get later in the year ... I'm more comfortable building something that runs inside of Linux so that's where my head is at really. The Epiphany chip is just a nice to have really, I'm more excited to play with the Zynq, the programming of the Epiphany is a bit over my head at the moment though in time I'd like to learn that too and see how far I can get with it. While the runs are small the Epiphany chips look pretty expensive for designing your own boards too. ($US595 for 8 processors ... not really DIY friendly at this stage)

The whole big.LITTLE architecture is also of interest for running this stuff inside Linux too, though I note that's really not where this thread is going ... sorry for offtopic ...
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Old 25th October 2013, 03:42 AM   #490
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Let's see how a WM8580 "multichannel audio codec cape" would connect on the XMC4500 Relax Lite Kit available from HITEX, costing 10 euro (without shipment and tax).

The WM8580 cape would feature a local quartz, connected to the WM8580.
The WM8580 features an internal PLL generating all audio clocks, including MCLK.
The WM8580 would act as I2S master, sending the I2S bit_clock and I2S frame_sync to the XMC4500.
Consequently, the XMC4500 doesn't see MCLK.

Viewed from the XMC4500 Relax Lite Kit :
Pin Header X2 delivers :
- two full-duplex I2S (slaves)
- one SPI (master)
Pin Header X1 delivers :
- one full-duplex I2S (slave)
It could be that hacking pin 17 and pin 19 on IC200 footprint, one may get as extra :
- one I2C

Thus, the XMC4500 Relax Lite Kit + WM8580 cape would implement a stereo 3-way Xover :
- taking one I2S as input (audio may come from the WM8580 SPDIF-in, or from the WM8580 stereo ADC)
- delivering three I2S as outputs (six line-level analog channels out).

Volume control would be done using the WM8580 output level registers.
There could be a connector for adding an external high quality multichannel volume control, such connector carrying SPI plus chip select, or I2C.

Asynchronous USB audio could come later on, using a second "cape" featuring a second XMC4500 dedicated to the USB protocol, requesting stereo audio samples with the same WM8580 still acting as local, master audio clock and multichannel DAC. One could add galvanic isolation at this stage.

What's your opinion about this?
Attached Images
File Type: png XMC4500 Relax Lite Kit.png (69.8 KB, 104 views)
File Type: png XMC4500 block diagram.png (72.7 KB, 103 views)
File Type: png XMC4500 Relax Lite Kit - USICs pinout.png (86.1 KB, 84 views)
File Type: png XMC4500 Relax Lite Kit - Pin Headers X2 and X1.png (95.4 KB, 81 views)
File Type: png WM8580 Block Diagram.png (89.6 KB, 85 views)

Last edited by steph_tsf; 25th October 2013 at 03:52 AM.
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