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Old 8th May 2013, 11:27 AM   #431
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This present thread is about Open Source. You may want a kind of poor man's DSP Concepts Audio Weaver, in Open Source.

Audio Weaver? | DSP Concepts

Look the screenshot. You see those blocks and those interconnections ?
Generate the schematic using LTspice. Create parts using LTspice. Interconnect them.

Relying on LTspice, there can't be bells and whistles like user-friendly configuration panels. As example, you'll need to edit the AGC or Limiter parameters using plain text, double-clicking on the part.

Grab the netlist from LTspice, in text format.

Deliver such netlist to a DSP board.

You are done.

Of course you need some DSP bootloader, operating system and scheduler running inside the DSP board. Such is the difficulty.
Attached Images
File Type: jpg DSP Concepts Audio Weaver.jpg (233.3 KB, 294 views)
Attached Files
File Type: zip WM8731-Audio-Crossovers-Digital-XOs.zip (9.4 KB, 14 views)

Last edited by steph_tsf; 8th May 2013 at 11:37 AM.
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Old 8th May 2013, 11:55 AM   #432
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XX100 $ADCL N001 $shift params: n=-8
XX902 N014 $DACL $shift params: n=+8
V1 in 0 AC 1 0
XX900 N012 N013 $db params: dB=-4.3
XX901 N013 N014 $delay params: n=5
XX999 in $ADCL NC_01 $DACL $DACR NC_02 NC_03 $wm8731me
XX905 N017 $DACR $shift params: n=+8
XX903 N015 N016 $db params: dB=-4.3
XX904 N016 N017 $delay params: n=5
XX400 N003 N004 N005 $split
XX200 N001 N002 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX300 N002 N003 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX500 N005 N006 $df2e params: a1=+1.33145199 a2=-0.50455703 b0=+0.04327626 b1=+0.08655252 b2=+0.04327626
XX600 N006 N008 $df2e params: a1=+1.33145199 a2=-0.50455703 b0=+0.04327626 b1=+0.08655252 b2=+0.04327626
XX700 N008 N010 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX800 N010 N012 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX501 N004 N007 $df2e params: a1=+1.33145199 a2=-0.50455703 b0=+0.70900225 b1=-1.41800451 b2=+0.70900225
XX601 N007 N009 $df2e params: a1=+1.33145199 a2=-0.50455703 b0=+0.70900225 b1=-1.41800451 b2=+0.70900225
XX701 N009 N011 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0
XX801 N011 N015 $df2e params: a1=0 a2=0 b0=+1 b1=0 b2=0

* block symbol definitions
.subckt $shift in out
E1 out 0 in 0 gain={2**n}
.ends $shift

.subckt $db in out
E1 out 0 in 0 gain={10**(dB/20)}
.ends $db

.subckt $delay in out
R2 N003 0 50
R1 N002 N001 50
T1 N002 0 N003 0 Td={n/Fs} Z0=50
E1 N001 0 in 0 1
E2 out 0 N003 0 2
.ends $delay

.subckt $wm8731me MICIN ADCL ADCR DACL DACR LHPOUT RHPOUT
R1 MICIN ADCL 1
R2 MICIN ADCR 1
R3 LHPOUT DACL 1
R4 RHPOUT DACR 1
.ends $wm8731me

.subckt $split IN OUT1 OUT2
R1 OUT1 IN 1
R2 OUT2 IN 1
.ends $split

.subckt $df2e in out
E2 N001 N004 N003 0 {a1}
E3 N004 0 N006 0 {a2}
E4 out N002 checkpoint 0 {b0}
E5 N002 N005 N003 0 {b1}
E6 N005 0 N006 0 {b2}
E1 checkpoint N001 in 0 1
XX1 checkpoint N003 delay_v
XX2 N003 N006 delay_v
.ends $df2e

.subckt delay_v in out
R2 N003 0 50
R1 N002 N001 50
T1 N002 0 N003 0 Td={1/Fs} Z0=50
E1 N001 0 in 0 1
E2 out 0 N003 0 2
.ends delay_v

.param Fs=44100
.ac oct 100 100 10k
* ;-)
* ;-)
.backanno
.end
Attached Images
File Type: jpg LTspice as graphical DSP front-end.jpg (285.7 KB, 292 views)
Attached Files
File Type: zip WM8731-Audio-Crossovers-Digital-XOs.zip (9.4 KB, 8 views)
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Old 15th May 2013, 03:37 AM   #433
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Energy Micro has some new M4s - here's a link to the Reference Manual - http://cdn.energymicro.com/dl/device...nce_manual.pdf

While the pricing doesn't look anywhere near as attractive as Freescale, they do include a fair chunk of RAM at the bottom end (32k) and the FPU. There are also 3 USARTs which can be operated in I2S mode - they also support some of the other serial audio formats too Top clock is only 48MHz though.
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Old 1st October 2013, 12:51 AM   #434
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Here's an interesting development - ADI, despite having their own IP in the form of the BlackFin (co-developed with Intel) has announced a Cortex M4 SoC : ADSP-CM402F datasheet and product info | ARM Cortex M4 Mixed-Signal Control Processor with Precision 16 bit ADCs in 14x14mm 120 lead LQFP | CM4xx Mixed-Signal Control Processors | Analog Devices

With a top spec'd speed of 240MHz, looks to be the fastest M4 to date. As regards I2S, the DS says these parts have '3 half-Sports' which can be configured into I2S mode. Perhaps the 'half' means only half duplex? Chip prices not yet released but the eval boards are $200-$300, the more expensive one coming with a Segger J-link.
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Old 1st October 2013, 06:00 AM   #435
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Blackfin is 16 bit so 32 bit processing takes quite a few clocks. The 32 bit data path and 80 bit MAC on the SHARCs is a more proper competitor to the M4's 32 bit data path and 64 bit MAC. A DSC like the M4 tends to be faster on IIR and DSPs like the SHARC faster on FIR and even fairly low normalized frequency biquads don't benefit from the extra 16 bits in the SHARC MAC. So it's logical diversification on the DSP side, greater flexibility of a microcontroller aside.

Each SPORT has SCLK, WCLK, and two data lines which can operate in either direction. From a quick look in the neighborhood of page 23-27 it sounds like the data lines are independent of each other. So with the four half sports on the 176 pin LQFP one could probably do one I2S in and three I2S out for, say, SPDIF receive and three way XO. Or USB in and four way XO.

If one opts for a part compatible with the SPORTs packed I2S format then IO is a non-issue for most scenarios. The CS4365 and CS4385 DACs and CS42526 and CS42528 codecs come to mind.

Interesting offering. Given the right tools and pricing it could be a viable alternative to NXP's LPC4300s for the mainline case where only one "codec"'s worth of IO is needed.
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Old 1st October 2013, 02:30 PM   #436
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Quote:
Originally Posted by twest820 View Post
Blackfin is 16 bit so 32 bit processing takes quite a few clocks. The 32 bit data path and 80 bit MAC on the SHARCs is a more proper competitor to the M4's 32 bit data path and 64 bit MAC. A DSC like the M4 tends to be faster on IIR and DSPs like the SHARC faster on FIR and even fairly low normalized frequency biquads don't benefit from the extra 16 bits in the SHARC MAC. So it's logical diversification on the DSP side, greater flexibility of a microcontroller aside.

Each SPORT has SCLK, WCLK, and two data lines which can operate in either direction. From a quick look in the neighborhood of page 23-27 it sounds like the data lines are independent of each other. So with the four half sports on the 176 pin LQFP one could probably do one I2S in and three I2S out for, say, SPDIF receive and three way XO. Or USB in and four way XO.

If one opts for a part compatible with the SPORTs packed I2S format then IO is a non-issue for most scenarios. The CS4365 and CS4385 DACs and CS42526 and CS42528 codecs come to mind.

Interesting offering. Given the right tools and pricing it could be a viable alternative to NXP's LPC4300s for the mainline case where only one "codec"'s worth of IO is needed.
Don't both parts use 16 bit multipliers and SIMD to execute a 32 bit multiply ? Neither execute a 32 bit multiply in one clock cycle.
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Old 1st October 2013, 02:36 PM   #437
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From ARM's Technical Reference Manual for the M4 :
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Old 1st October 2013, 03:14 PM   #438
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Quote:
Originally Posted by abraxalito View Post
From ARM's Technical Reference Manual for the M4 :
Is that for a 16 bit multiply or 32 bit ? Apparently its floating point performance apparently is not that good,

Quote:
DSP operations can use either floating point or fixed point format. The Cortex M4 core has optional hardware support for 32 bit floating point, but is not optimized for DSP algorithms and too slow for most DSP applications.

Last edited by Trevor White; 1st October 2013 at 03:17 PM.
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Old 1st October 2013, 04:07 PM   #439
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Trevor, arm_biquad_cascade_df1_q31 and arm_biquad_cas_df1_32x64_q31 are built around SMLAL. You can find specifics in the links and a bit more context on the DSP requirements in this post, though the questions you're asking would be best answered by spending some time with the instruction set and DSP library documentation for the respective processors.

A 200ish MHz single M4 core more or less by definition can't compete with a 450MHz dual core SHARC, much less the TigerSHARCs. But, as I've remarked earlier on this thread, an M4 around 75MHz is sufficient for pretty rich IIR based XO and EQ on 24/44.1 audio---more typical configurations could run in 25MHz or less. At full clock the faster M4s are comparable to the low end SHARCs used in things like Peavey's Vypyr modeling amplifiers and a pair of them isn't that far off the dual Blackfins Fractal Audio had in the original AxeFX. So the bang for the buck on an M4 that's $9 or less in DIY quantities and uses a free development environment with $20 or less of debug hardware is high compared to $4k or so entry cost for SHARC tooling. I'm curious to see where Analog positions the M4 along the SigmaDSP to SHARC continuum; wouldn't be entirely surprising if the M4 ends up being a SigmaDSP replacement.
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Old 1st October 2013, 09:24 PM   #440
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Quote:
Originally Posted by Trevor White View Post
Is that for a 16 bit multiply or 32 bit ?
32bit which can generate either a 32bit or 64bit result. There's no 16bit multiply though from memory there might be a dual (i.e. in parallel) 16bit multiply instruction.

Quote:
Apparently its floating point performance apparently is not that good,
Where did you get your quote?
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